Product category:
Communications ICs (Wired)
News Release from: Agere Systems | Subject: PayloadPlus
Edited by the Electronicstalk Editorial
Team on 31 October 2003
Network processor simplifies
multiservice platform
Calix set out to improve voice, data, and video service delivery economics for wireline carriers of all sizes, with the creation of its C7 simplified services platform.
Calix set out to improve voice, data, and video service delivery economics for wireline carriers of all sizes, with the creation of its C7 simplified services platform Agere Systems and its PayloadPlus traffic management network processor, played a key role in helping Calix successfully achieve its goal
This article was originally published on Electronicstalk on 30 Jun 2003 at 8.00am (UK)
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The Calix C7 platform integrates the functionality of a broadband digital loop carrier, digital subscriber line access multiplexer, next-generation synchronous optical network multiplexer, Internet protocol router, Ethernet, and asynchronous transfer mode (ATM) switches into a single equipment platform.
To deliver on all of these network applications, Calix needed a network processor that could provide wire-speed performance with a flexible programming environment and simultaneously support many different communication protocols.
Agere's network processor was a strategic fit for Calix because of its ability to perform packet/cell classification, policing, operations, administration and maintenance (OAM), and statistics gathering.
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Agere's solution also provides critical traffic management capabilities: queuing, buffer management, traffic shaping and packet modification.
These functions allow Calix to support multiprotocol traffic and at the same time provide valuable flow isolation with differential bandwidth constraints.
During the development of the C7, Calix and Agere encountered several design challenges.
One was how to squeeze more functionality into such a small amount of space without dramatically increasing costs.
Another was how to handle a combination of circuit switched, cell switched, and packet switched network traffic, both from a backplane switch fabric and line card point of view.
To meet these multiservice objectives, Calix implemented two fully custom ASICs to interoperate with the Agere network processor in a glueless fashion.
The custom ASICs provided the flexible switch functionality.
The network processor provided packet/cell services such as header translation, queuing, scheduling, segmentation and reassembly and various other traffic management features.
The tight integration between Agere's network processor and Calix's ASICs provided unprecedented capacity in a very compact space.
This allowed Calix to fit up to five of its platforms into a single standard 7ft central office rack space.
Calix also required a network processor architecture that could readily scale to support 10Gbit/s of wire-speed functionality per slot and still be able to handle a fully flexible multiservice capability.
The Agere network processor architecture provided the right balance between hardwired and programmable functionality to allow effective scaling from below 1.2 to more than 10Gbit/s of full-duplex aggregate throughput per trunking unit.
Agere also helped Calix consolidate line unit functionality.
With Agere's network processor technology, Calix's common control line cards can optionally integrate redundant trunking line unit functionality.
This frees up two extra line card unit slots for additional service usage-all on the same C7 platform.
More available service slots for service usage translate to more feature-rich line unit possibilities.
Any service slot can host the following: an (x)DSL unit DSLAM; a POTS unit (digital loop carrier); an OC-48/12/DS3/T1 (add/drop multiplexer/DCS); OC48 T1 IMA (ATM switch); GE/FE (switch/router); and OLT line unit (FTTP access).
The Calix switch architecture, together with Agere's technology, allowed the central switching function to remain simple, while exporting wire-speed intelligence to the line/trunking units.
This is where the network processor typically resides.
The line units that populate the chassis determine the aggregate capability of the platform configuration.
The centralised switch provides raw inter-worked capacity, while the line units provide various degrees of value added features.
Some simpler subscriber service line units may operate without the need for a local network processor, while other more complex line units may.
This permits a mix and match of line card units, allowing system capability to be optimally tailored.
The capabilities of the Agere network processor and the raw capacity of the Calix switch both had to allow significant simplification of the subscriber line units.
This simplification was needed for Calix to provide a cost-effective platform solution that could serve simple network element functionality, such as DSLAM.
In a DSLAM application, the Agere network processor functions as a centralised switch.
Because Agere's network processor can feed multiple DSL line cards, each with many ports, the DSL line card is both less complex and inexpensive.
This allows more rapid design optimisation of the most cost sensitive system components.
Agere's network processor solution offers fully programmable traffic management capabilities, including buffer management policies, through a reduced and optimised C instruction set.
To enforce a buffer management policy in the Calix equipment, short script executes on the buffer management-processing engine.
The traffic management script determines whether to discard or allow traffic to be scheduled.
This decision is based on the user programmed discard policy.
In addition, Agere's network processor has the facilities to schedule cell and frame-based traffic using a number of scheduling algorithms.
The traditional ATM constant bitrate (CBR), variable bitrate (VBR) and unspecified bitrate (UBR) schedulers are programmable in Agere's network processor.
Traffic scheduling and shaping are defined by the network processor's scheduling logic and programmable queue definitions.
The internal logic provides the high-level control of network processor scheduling functions.
The processor's configuration, the traffic shaper compute engine, and the programmable queue definitions define the traffic shaping.
The traffic shaper compute engine executes a program defined at every scheduling event.
The traffic shaper is also used to support class of service queue selection for frame-based traffic using algorithms such as weighted round robin; variable-bitrate cell-based traffic scheduling using dual leaky bucket algorithms; and frame-based, smoothed, deficit-weighted, round robin scheduling by tracking rate credits for each queue.
The programmability and flexibility of Agere's processor combined with Calix's innovative design made it possible to successfully build an advanced multiservice access platform that integrates many different functions into a single enclosure.
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