Ethernet over Sonet mapper integrates more

The HDMP-3002 gigabit Ethernet over Sonet (EoS) mapper chip is the first to integrate serdes, clock data recovery and OC-3 to OC-48 framers.

The HDMP-3002 gigabit Ethernet over Sonet (EoS) mapper chip is the first to integrate serdes, clock data recovery and OC-3 to OC-48 framers, three features required to efficiently format data for Sonet/SDH networks.

The new chip is expected to save network equipment manufacturers design and test time, board space, power consumption and system costs.

The Agilent HDMP-3002 is the second member of Agilent's multiprotocol IC (MPIC) family.

MPICs take protocol independent traffic and map it into Sonet/SDH, providing a simple solution for loading enterprise data traffic onto a Sonet/SDH metro infrastructure.

"We are applying our IC expertise and strength in enterprise and Sonet/SDH networking to deliver a family of industry-leading multiprotocol ICs to network equipment manufacturers", said Philip Gadd, IC marketing manager for Agilent's ASSP Products Division.

"Agilent's new EoS mapper chip significantly reduces the cost of transporting enterprise data over the legacy Sonet/SDH infrastructure, satisfying the needs of corporate users and service providers".

The Agilent HDMP-3002 provides full-duplex mapping of Fast Ethernet and Gigabit Ethernet frames encapsulated into STS-48/12/3 Sonet/SDH payload using the generic framing procedures (GFP), frame delineated HDLC (per RFC 1662/2615), or the link access procedure-SDH (LAPS) protocol.

The device can connect up to four gigabit Ethernet feeds into one STS-48/STM-16 (2.488Gbit/s), four STS-12/STM-4 (622Mbit/s), or four STS-3/STM-1 (155Mbit/s) channels.

Its virtual concatenation feature allows service providers to dial up "bandwidth on demand" for customers, allocating bandwidth data streams as small as STS-1 (51.8Mbit/s) granularity.

Virtual concatenation eliminates the bandwidth inefficiency and long provisioning delays of legacy Sonet/SDH transport networks.

The Agilent HDMP-3002 is part of Agilent's METRAK family of fibre-optic transceivers and ICs aimed at metropolitan network applications.

It is designed for use in multiservice provisioning platforms (MSPPs), edge routers and line cards for Sonet add drop multiplexers (ADM) within the LAN and metropolitan access (edge) network.

The edge network is where the carrier-owned WAN meets the corporate-owned LAN.

Agilent's EoS mapper provides access to Sonet/SDH overhead collection, allowing carriers to manage their networks.

It also offers the performance monitoring carriers require without the need for costly layer-3 processing.

Agilent's EoS mapper is a highly integrated, layer-2, single-chip solution that is implemented in a low-power 0.18-micron CMOS process with a 1.8V core, and both 2.5 and 3.3V I/Os.

The device is supplied in a 664-pin ceramic ball grid array (CBGA) package and supports the OC-48/STM-16 (2.5Gbit/s) standard.

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