Embedded serdes squeezes in more channels

Agilent Technologies is claiming a breakthrough with its new 0.13-micron embedded serdes IP semiconductor core.

Agilent Technologies is claiming a breakthrough with its new 0.13-micron embedded serialiser/deserailiser (serdes) intellectual property (IP) semiconductor core.

The new IP core offers low power consumption and the lowest possible jitter available, enabling Agilent to integrate as many as 150 serdes channels onto a single ASIC, each operating at up to 3.125Gbit/s.

The breakthrough IP core enables the integration of more serdes channels onto a single chip than previously possible.

The integration of multiple channels also will allow network equipment manufacturers increased reliability and reduced size, complexity and cost of serdes system designs, used to enable next-generation high bandwidth networking and storage systems.

Agilent's ASIC capability is based on a heritage of high transistor ASIC designs with extremely high serdes channel count.

Previously, Agilent integrated more than fifty 2.5Gbit/s transmit and receive channels on a single CMOS chip and subsequently produced an ASIC with 36 multirate serdes channels operating at up to 3.125Gbit/s.

Agilent's new embedded serdes core exhibits the industry's lowest jitter performance.

The jitter performance specification is a critical measure of how well network elements operate - the lower the jitter, the better.

Any phase variations or jitter induced in the network can cause a degradation of transmission quality, bit errors, and data loss.

At less than 2ps RMS, the new Agilent serdes core provides random jitter performance that will support bit error rates (BER) of better than 10e-17 for network equipment backplane applications.

BER indicates how often a bit will be misinterpreted, and lower BER results in more reliable and consistent data transmission.

Agilent offers the new 0.13-micron serdes core in pairs, triplets, or octets that can be combined in a very high channel-count chip.

The low power core features 75mW typical operation and is XAUI, Fibre Channel, and InfiniBand compliant.

It also features a selectable reference clock, and supports both backplane and chip-to-chip applications.

The maximum usable runlength (defined as a string of consecutive 1s or 0s) is in excess of 100bit, which exceeds Sonet/SDH requirements.

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