Core decodes IEEE Turbo Product Codes

Comtech AHA Corp has developed an IEEE802.16a compliant Turbo Product Code (TPC) decoder core.

Comtech AHA Corp has developed an IEEE802.16a compliant Turbo Product Code (TPC) decoder core.

The core implements the same code shortening schemes as in the IEEE802.16a standard.

TPCs are also referred to as Block Turbo Codes (BTCs) in the 802.16a standard and are necessary for noisy application environments where higher performance FEC is required.

Coding gain in a typical system is very substantial when compared to a Reed Solomon-Viterbi concatenated solution.

This coding gain afforded by TPCs can be used by the system designer to offer increased range of wireless communications or decreased power requirements.

Features include a fully synchronous, one clock, one edge design and supports all IEEE802.16a standard BTC coding options.

Latency is less than two FEC blocks and the core is programmable for up to 256 iterations per block.

It supports channel rates up to 60Mbit/s with three iterations and a 150MHz clock.

RAM interfaces support synchronous or asynchronous designs.

The core also features a JTAG controller for test.

Deliverables will include an IEEE802.16a compliant TPC core VHDL and/or Verilog net list, timing constraints (Design Compiler and Ambit format), test bench and verification vectors (VHDL), a bus functional model, and TPC core software (C/C++ model).

The TPC core has been proven with working silicon implementations in the field today.

A fully compatible TPC encoder core is also available.

Pricing and lead-times will vary depending on specific customer requirements.

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