Product category:
Intellectual Property Cores
News Release from: Comtech AHA Corp
Edited by the Electronicstalk Editorial
Team on 26 January 2007
LDPC IP core to test satellite comms
The Mitre Corporation has selected Comtech AHA's Low Density Parity Check (LDPC) coding technology to demonstrate the effectiveness of LDPC on the High Data Rate Test Waveform.
The Mitre Corporation has selected Comtech AHA's Low Density Parity Check (LDPC) coding technology to demonstrate the effectiveness of LDPC on the High Data Rate Test Waveform This will enable the US Government to further assess the use of LDPC technology across the US military's next generation satellite communications programmes
This article was originally published on Electronicstalk on 2 Mar 2001 at 8.00am (UK)
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Cost-effective forward error correction
Advanced Hardware Architectures (AHA) has developed what it claims is the most cost effective forward error correction (FEC) integrated circuit ever produced.
Engineers at Comtech AHA worked directly with systems engineers at the Mitre Corp to create a new powerful LDPC coding structure that offers near optimal performance for the code rates and block size specified, while meeting the strict datarate and FPGA resource requirements of the Test Waveform.
"Comtech AHA has a long history of offering high performance forward error correction technology".
"This latest LDPC solution clearly surpasses the performance and FPGA resource requirements of the High Data Rate Test Waveform", said Jose Torres, Principal Signal Processing Engineer at the Mitre Corporation.
Comtech AHA's AHA4703 LDPC IP core will fit into the Xilinx Virtex II Pro family of FPGA devices and achieves datarates above 34Mbit/s for all codes.
It supports three unique code rates with a fixed data block sise of 12Kbit.
The AHA4703 LDPC IP core can readily support additional FPGA families.
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