Low-power design successfully validated

Accent has successfully validated a low-power design flow using the Cadence Encounter digital IC design platform and ARM Artisan physical IP.

Accent has successfully validated a low-power design flow using the Cadence Encounter digital IC design platform and ARM Artisan physical IP.

The design flow targets low-power IC design and was proven on a design comprising a large portion of an SoC for a wireline application.

Using the ARM Artisan Metro low-power IP with multivoltage and multithreshold capabilities, the design was implemented with a multisupply multivoltage (MSMV) design flow using three power domains.

High voltage threshold (low leakage) optimisation was performed on both the MSMV implementation and a baseline implementation with a single supply voltage to further reduce leakage power.

compared with the baseline design flow, the low-power design flow reduced dynamic power by 34%.

Additionally, the low voltage section of the design also showed 40% less leakage power than the baseline flow implementation.

As a result, Accent was able to perfect a methodology that implements multivoltage capabilities in new designs and to compute tradeoffs in power consumption.

"The need to accommodate multiple power domains and multiple voltage levels makes low-power chip design much more complex than normal chip design", said Claudio Fasce, Vice President of Business Area Design and Supply Chain Management Services for Accent.

"Using the Cadence Encounter platform and the ARM Metro IP supporting MSMV design, we were able to quickly validate our low-power design flow and significantly improve our overall low-power design methodology".

"Close collaboration with ARM and Cadence expands our design skills and enables us to deliver better performing devices and greater competitive advantage to our customers".

The Encounter low-power flow provides complete support for multiple supply voltage designs.

It consists of top-down multisupply voltage synthesis using Encounter RTL Compiler global synthesis.

This is followed by Encounter implementation for low-power and accurate SI- and IR-aware timing signoff with CeltIC Nanometre Delay Calculator (NDC) and VoltageStorm static and dynamic power analysis.

"We continue to focus on our commitment to customer success", said Wei-Jin Dai, Platform Vice President, Digital IC Implementation at Cadence.

"This project proves the production readiness and quick turnaround capabilities of the Encounter low-power design flow".

"Through our broad, deep collaboration with design chain leaders such as ARM and leading-edge design houses such as Accent, we are able to continue advancing low-power design into the mainstream".

The ARM Artisan Metro low-power platform provides a comprehensive solution for dynamic and leakage power reduction, and makes high-density, yield-improved designs possible.

The platform includes standard cells, memories, I/Os and multivoltage kits.

All components take advantage of new process, circuit design, voltage scaling, power-aware EDA tools and chip-level design techniques to enable designers to meet the growing need for power dissipation control.

"ARM is committed to extensive validation of our physical IP in design flows", said Neal Carney, Vice President of Marketing, Physical IP, ARM.

"The team efforts of ARM, Accent and Cadence have substantiated power reduction capabilities and techniques that continue to build on the results of the Silicon Design Chain low-power initiative that will greatly benefit our mutual customer base".

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