Product category:
Communications ICs (Wired)
News Release from: Analogix Semiconductor | Subject: D-PHY 5G
Edited by the Electronicstalk Editorial
Team on 12 August 2004
Serdes chips speed through legacy
backplane test
Analogix Semiconductor has completed testing its 6.25Gbit/s serdes chips using Tyco Electronics' HM-Zd legacy backplane system.
Analogix Semiconductor has completed testing its 6.25Gbit/s serdes chips using Tyco Electronics' HM-Zd legacy backplane system The Analogix D-PHY 5G backplane transceiver maintained error-free signals at extended trace distances of up to 56in in a set of rigorous tests simulating real-world conditions
This article was originally published on Electronicstalk on 12 Apr 2004 at 8.00am (UK)
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The tests took into account key design variables in both backplanes and serdes chips.
On the backplane side, the Tyco Electronics HM-Zd legacy backplane systems offered a reference platform with: inexpensive FR-4 circuit-board material; low-cost, easy-to-use connectors; short and extended trace lengths on both the daughtercards and backplane; and the absence of additional performance- enhancing techniques, such as back drilling.
On the serdes side, the Analogix D-PHY 5G family was tested with multiple data patterns, raw and encoded data, and multiple channels operating.
Ted Rado, Analogix Vice President of Marketing, said: "The copper-based backplanes in today's systems weren't built to deal with noise levels that emerge at speeds of 5Gbit/s and up.
Yet designers are pressured to keep boosting performance within the limits of these original backplanes".
"So it is absolutely critical when testing new devices to put ourselves in the shoes of the system designer, and set up a test environment that mirrors his world.
That world has a huge potential for noise generation, with long, narrow line-card and backplane traces, common legacy materials and the lack of costly 'luxury' processes such as back drilling to reduce noise".
"Tyco Electronics' HM-Zd connectors and reference platform provide an excellent way to show how a vendor's serdes solution can perform under realistic system-level testing conditions".
John D'Ambrosia, Manager of Semiconductor Relations at Tyco Electronics, said: "The HM-Zd Legacy backplane was designed to test emerging 6.25Gbit/s devices in an environment that is representative of backplanes in the field today".
"The use of higher-performance materials, selective layer routing, or back drilling optimise the performance of the test backplane channel and minimise the challenges that a device will face during testing such as this, as opposed to operating conditions in the real world".
"Analogix used our HM-Zd legacy platform to subject its new products to extremely stringent testing".
"The D-PHY devices were put through their paces at the highest possible bit rate under full-duplex conditions using both encoded and unencoded data".
"Truly impressive results, in terms of the distances over which the devices maintained truly error-free signal integrity, were achieved".
Separate scenarios for encoded and unencoded data were run on Analogix's D-PHY 4x5G quad transceiver, with all four high- speed links running at 6.25Gbit/s (an aggregate 25Gbit/s full- duplex transmission).
In the first test, using PRBS 31 (pseudorandom bit sequence) unencoded data, the D-PHY 4x5G drove signals 42in over: two 10in line-card traces, a 16in backplane trace, two Tyco HM-Zd connectors and a 6in Analogix evaluation board; and two 2.5in line card traces, a 30in backplane trace, two connectors and a 6in evaluation board.
In the second test, using CJPAT (continuous jitter test pattern) encoded data, the D-PHY 4x5G device drove signals 56in over two 10in line card traces, a 30in backplane trace, two connectors and a 6in evaluation board.
All tests ran error-free for more than seven days, correlating to bit error rates of 10e-16 or better.
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