Product category:
Communications ICs (Wired)
News Release from: Analogix Semiconductor
Edited by the Electronicstalk Editorial
Team on 22 October 2004
Serdes solutions work together
Analogix Semiconductor and Synopsys have successfully completed interoperability testing of their serdes solutions over Tyco Electronics' HM-Zd Legacy Backplane System.
Analogix Semiconductor and Synopsys have successfully completed interoperability testing of their serdes solutions over Tyco Electronics' HM-Zd Legacy Backplane System, a reference platform that uses standard, inexpensive FR-4 circuit-board material The Analogix and Synopsys serdes were able to maintain sustained error-free full-duplex communication at rates up to 6.25Gbit/s over trace distances of more than 40in of standard FR-4 backplane material
This article was originally published on Electronicstalk on 12 Apr 2004 at 8.00am (UK)
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Analogix Semiconductor has completed testing its 6.25Gbit/s serdes chips using Tyco Electronics' HM-Zd legacy backplane system.
Proven interoperability provides system designers with increased flexibility in designing the most efficient, lowest-cost systems possible.
The demonstration is the first to prove the multi-vendor interoperability of serdes solutions that are designed to support next-generation interconnect standards, including the OIF CEI-6G Long Reach Interoperability Agreement, Next- generation Rapid I/O, Serial ATA (SATA), Serial Attached SCSI (SAS) and PCI Express Generation 2.
The two devices tested were Analogix's D-PHY 4x5G, a discrete backplane transceiver capable of 1.25 to 6.25Gbit/s transmission; and an ASIC containing a Synopsys 6.25Gbit/s serdes, a decision feedback equalisation (DFE)-enabled NRZ (binary) core capable of 622Mbit/s to 6.25Gbit/s transmission.
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The two interoperated over Tyco Electronics' Legacy HM-Zd backplane.
"Standards efforts are critical in accelerating the process by which different vendors achieve interoperability", said Ted Rado, Analogix Vice President of Marketing.
"But, with the design complexities of leading-edge, high-speed technologies, meeting standards often is not sufficient - especially when those standards are still early in the specification stage".
"Multivendor testing is key to providing the proof of device compatibility that customers want".
"Highly interoperable and reusable standards-based mixed- signal IP cores are essential to enable adoption of faster interconnect solutions up to 6.25Gbit/s and beyond", said Bill Hoppin, DesignWare Mixed-signal IP Business Development at Synopsys.
"This interoperability demonstration gives designers confidence that our DesignWare serdes technology has the robustness and margin needed to achieve true interoperability at 6.25Gbit/s over difficult backplane applications".
John D'Ambrosia, Manager of Semiconductor Relations at Tyco Electronics, said: "The HM-Zd Legacy backplane was designed to rigorously test emerging 6.25Gbit/s devices in an environment that is representative of copper-based backplanes in the field today".
"This test shows that serdes solutions from Synopsys and Analogix can deal with problems such as reduced signal-to-noise ratios that emerge at speeds of 5Gbit/s and up, and that they can do so while communicating with each other over a single backplane".
In the test, conducted at Analogix, PRBS 31 (pseudorandom bit sequence) unencoded data ran at 6.25Gbit/s.
The Analogix D- PHY 5G transmitter drove the Synopsys receiver and vice versa, realising 50Gbit/s over four full-duplex, 40-plus-inch FR-4 links (30in backplane trace plus 6in line-card trace plus 6in evaluation-board trace).
The devices were operated in both synchronous and asynchronous modes.
The test ran error-free, validating bit error rates (BER) of 10e-15 or better, and, using diagnostic capability integrated into the Synopsys core, extrapolated BER to greater than 10e-18.
Tyco Electronics' HM-Zd Legacy Backplane System, introduced in July 2003, provides a common, defined environment for interoperability and performance testing of solutions for designs using low-voltage differential signalling.
Based on Nelco 4000-6 material, it provides 16 full-duplex paths per three channel lengths of 1, 16 and 30in, and implements differential pairs based on a 0.006in trace width.
Furthermore, to mirror implementations in the field today, no stub removal techniques, such as backdrilling, have been implemented in the connector area.
Analogix's D-PHY family of backplane transceivers uses advanced analogue signal conditioning techniques to eliminate the signal-integrity problems that characterise high-speed data transmission over copper media.
D-PHY products drive increased performance through existing backplane traces while interoperating with existing line cards.
The D-PHY family is designed for use in enterprise switches and routers, carrier- class transport equipment, Fibre Channel and IP-based storage systems, and high-end servers.
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