Design software to create cell libraries

Characterisation products Liberate and Variety have been adopted by STARC, the Japanese Semiconductor Technology Academic Research Center.

Altos Design Automation has announced its characterisation products Liberate and Variety have been adopted by STARC, the Japanese Semiconductor Technology Academic Research Center.

STARC is developing a manufacturing-aware design methodology named STARCAD-CEL that addresses the challenges of very advanced semiconductor process technologies including 65nm, 45nm and 32nm.

The STARCAD-CEL design methodology will be shared amongst the top Japanese semiconductor companies that comprise STARC's membership as a standard digital design platform.

Within this flow, STARC will use Liberate to create libraries for design implementation including ECSM and CCS timing, noise and power views.

Variety will be used to build libraries for statistical timing analysis (SSTA) signoff.

Nobuyuki Nishiguchi, Vice President and General Manager at STARC says: "Fundamental to any digital implementation design methodology is the cell library that encapsulates the underlying electrical characteristics of the target process technology".

Nishiguchi continues: "We selected the Altos products because of their remarkable performance and their ability to support multiple vendors flows especially for statistical timing models".

"These are essential to manage variation at 45nm and below".

"STARC performs a very thorough evaluation of every component that comprises their STARCAD-CEL design methodology", says Jim McCanny, Altos CEO.

"To have our products selected by STARC represents a major milestone in Altos' short history and represents validation of our technology and roadmap".

"Quality library models, generated with high efficiency, are vital to maximising the potential of advanced ultra nanometer silicon process technology".

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