Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: AMI Semiconductor | Subject: XPressArray
Edited by the Electronicstalk Editorial
Team on 23 January 2002
Array aimed at FPGA conversions
AMI Semiconductor (AMIS) has launched a 0.18-micron hybrid gate array for medium-density high-speed 1.8V ASICs and FPGA-to-ASIC conversions.
AMI Semiconductor (AMIS) has launched a 0.18-micron hybrid gate array for medium-density high-speed 1.8V ASICs and FPGA-to-ASIC conversions AMIS reckons the new array drastically reduces time to market and unit cost while providing customers with NRE (nonrecurring engineering) cost savings of up to 70%
This article was originally published on Electronicstalk on 26 Nov 2002 at 8.00am (UK)
Related stories
ASIC technology aims for budget FPGA replacement
AMI Semiconductor has outlined the next phase in the roadmap for its high-performance, low-power hybrid gate array solutions with the launch of a 1.5V version of its popular XPressArray technology.
Process boosts structured ASIC density
With more than two million fully programmable gates plus memory, the higher-density XPressArray (XPA-HD) offers 40% more density than AMI Semiconductor's existing XpressArray offering.
The new XPressArray platform also represents the industry's first drop-in replacement solution for converting 1.8V Xilinx Virtex-E and Altera APEX-E FPGAs to higher performance, lower power and more cost effective ASICs.
Operating with system clock speeds up to 250MHz, and local clock speeds up to 350MHz, XPressArray devices are available in a variety of package options.
The devices are fabricated using a hybrid process that integrates a leading 0.18um front-end process from TSMC with a proven AMIS metal finishing technology.
Further reading
Structured ASICs aim for frugal FPGA replacement
The XPressArray-II (XPA-II) is the newest addition to the market leading XPressArray structured ASIC family.
Clock generators for embedded communications
AMI Semiconductor (AMIS) has expanded its clock generator product line with a broad family of low-cost 1- and 2-phase-lock loop (PLL) clock ICs.
Clock generator saves space in portable designs
AMI Semiconductor (AMIS) has introduced a low-cost clock generator that will save space and reduce component count in high-performance MPEG-2 applications such as DVD players.
Similar to FPGAs, the TSMC processing expenses for prefabricated base array slices are shared across many applications.
For each customised application, the AMIS metal tooling and manufacturing costs are significantly lower than for 0.18um cell-based processes, resulting in the low NREs, low unit costs and fast cycle times associated with gate array metal finishing.
"TSMC is pleased to begin shipping XPressArray devices to AMIS today, and both companies are interested in seeing AMI Semiconductor's silicon proliferate throughout the market.
By selecting TSMC's 0.18um process as the foundation for this hybrid technology offering, AMI Semiconductor has demonstrated the easy adaptability of our foundry process to new applications with widespread potential", said Dr Kenneth Kin, TSMC senior president of worldwide marketing and sales.
Commenting at the launch of the hybrid gate array, Christine King, AMI Semiconductor's CEO states: "We have created a whole new approach to ASIC development that delivers the performance and low-power operation of more advanced processes without any of the cost or cycle time penalties associated with 'bleeding edge' technology.
In some cases, this could mean customers can reduce their NRE costs by as much as 70%, with a total cycle time, from netlist to prototype, as low as six weeks".
AMIS sees the XPressArray platform being particularly popular for OEMs wishing to convert FPGAs to ASICs where it can be used to create true pin-for-pin drop-in replacements or can help to reduce size and component count by converting multiple FPGAs to a single XPressArray gate array ASIC.
Vince Hopkin, vice president of Digital ASICs at AMIS, comments: "Cost reduction of FPGA designs is now a major issue and demand for FPGA-to-ASIC conversions is increasing.
At the same time, FPGA devices are using ever-smaller process geometries and lower operating voltages in the quest for higher density, higher performance and lower power.
To match operating voltage while providing better performance and power consumption characteristics an equivalent ASIC needs to be fabricated in a similar process technology.
The AMIS XPressArray hybrid architecture offers a novel solution to the challenges of maintaining FPGA process compatibility while delivering ASIC technology with reasonable NREs and low unit price".
He adds: " Featuring a proprietary device architecture that maximises 0.18um usage and achieves high logic density, ASICs based on the new hybrid technology achieve higher densities, improved performance and lower power consumptions than FPGAs operating at the same voltage".
AMIS also believes XPressArray devices meet the need for medium density ASIC 0.18um designs that have been priced out of the traditional cell-based market.
XPressArray hybrid gate array devices offer densities of up to 2.6 million gates, up to 200k internal registers, and between 31Kbit and 1.4Mbit of embedded configurable and initialisable memory.
Flexible I/O configurations include support for a wide variety of common standards including LVTTL, LVCMOS, PCI, HSTL, SSTL, GTL/+, LVPECL, LVDS and BLVDS.
The technology is compatible with 1.8, 2.5, 3.3 and 5.0V I/O schemes, while comprehensive clock management circuitry includes options for up to 12 all digital delay-locked loops (DLLs) and a maximum of four phase-locked loops (PLLs).
Embedded scan test logic is included to facilitate high fault coverage testing.
Rapid access to the XPressArray hybrid gate array technology can be achieved using the AMIS NETRANS FPGA-to-ASIC conversion methodology.
In addition, XPressArray synthesis libraries are available for leading commercial synthesisers such as Synplicity, Synplify ASIC and Synopsis Design Compiler.
Using the AMIS RTL hand-off flow tool, designers can submit RTL descriptions, scripts and timing constraints and AMIS will check, synthesise, layout and achieve timing closure of the design.
(This was Electronicstalk's Top Story on 22 January 2002).
(This was Electronicstalk's Top Story on 22 January 2002).
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