USB interface and microcontroller design kit

AMI Semiconductor (AMIS) has launched a comprehensive IP-based design and development kit that will significantly simplify the integration of robust USB interfaces into SoC solutions.

AMI Semiconductor (AMIS) has launched a comprehensive IP-based design and development kit that will significantly simplify the integration of robust USB interfaces into SoC solutions.

Suitable for both initial ASIC designs and FPGA-to-ASIC conversions, the AMIS USB interface and microcontroller design kit speeds the implementation of USB-based peripherals by providing all of the IP, supporting tools and documentation that the developer needs to quickly and easily deliver a complete USB device.

The new kit offers a complete USB development solution by combining configurable, modular RTL code descriptions of the USB interface engine and other key USB device design blocks with a simulation testbench that features test and verification scripts and a USB test host.

While it is supplied as standard with an R8051 8bit RISC microcontroller core, full compatibility with other third party microcontrollers ensures that the kit is also suitable for developers who have already chosen their microcontroller.

Fully compatible with version 1.1 and 2.0 of the USB serial bus specification as a slow or full speed device, the RTL blocks supplied in the USB interface kit can be easily integrated into a wide variety of USB device configurations.

Design is further simplified using the kit's proprietary USB test host RTL module that aids the rapid identification and rectification of bugs by providing all standard host functionality as well as allowing designers to inject error sequences onto the USB.

The USB test host module, along with most of the other USB device modules, is implemented as synthesisable RTL.

As a result, the modules can be used in both software simulation and in hardware prototypes.

Configurable RTL modules supplied with the kit include the USB interface engine state machine that handles all low-level USB protocol functions and monitors the status of addressed endpoint buffers in the endpoint group.

This machine also manages the transfer of USB data between endpoint buffers and the USB port.

All of the endpoint buffers are implemented with a single dual-port RAM contained within the endpoint group RTL module.

Each of the endpoints in the endpoint group are fully configurable based on the configuration selected by the host from the configuration tables contained in the microcontroller firmware.

The USB device architecture can support up to 31 fully configurable USB endpoints.

Other hardware features of the USB device include external microcontroller ports, a DLL clock generator and a USB transceiver pad that sources and sinks serial USB data from the USB interface.

Based on the 80C51 microcontroller, the R8051 core is a fully functional 8bit RISC embedded microcontroller developed for ASIC and FPGA implementations.

The RISC architecture allows the microcontroller to execute instructions up to 12 times faster than was possible with the standard 8051 architecture.

The core incorporates an 8bit control unit, an 8bit arithmetic unit and two 32bit I/O ports.

An internal data memory interface can address up to 256byte of read/write data memory space, while an external memory interface can address up to 64Kbyte of external program memory.

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