Product category:
Power Supply ICs and Controllers
News Release from: AMI Semiconductor | Subject: I3T50 smart power
Edited by the Electronicstalk Editorial
Team on 20 May 2003
Deep trench isolation shrinks smart
power SoCs
A new high-voltage mixed-signal technology reduces component count and cost and delivers high-density ASICs with chip areas that are up to 40% smaller than previous SoC solutions.
A new high-voltage, mixed-signal technology from AMI Semiconductor (AMIS) reduces component count and cost and delivers high-density ASICs with chip areas that are up to 40% smaller than previous SoC solutions The new I3T50 smart power technology will simplify the implementation of designs requiring high-performance, compact and robust ASICs and ASSPs and operation up to 50V
This article was originally published on Electronicstalk on 26 Mar 2001 at 8.00am (UK)
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The second in AMI Semiconductor's series of I3T mixed-signal technologies, I3T50 allows designers to integrate complex digital and precision analogue circuitry, embedded microprocessors, and high-voltage functionality into a single IC.
The result is a technology that is ideal for a variety of applications such as sensor interfaces, transceivers, and actuator and motor drivers.
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In developing its I3T50 technology AMIS has employed a proprietary deep trench isolation (DTI) technique that allows isolation distances between an ASIC's high-voltage devices to be dramatically reduced.
Because of this, the chip area of an I3T50 ASIC or ASSP is between 10 and 60% lower than SoC solutions that use standard junction isolation schemes.
I3T50 offers logic gate densities of 15,000/mm2 and can be used to create smart power SoC devices with gate counts as high as 500,000.
In addition to the digital logic, these devices can incorporate high-voltage circuitry such as motor controller drives, DC/DC convertors, and high-precision analogue circuits including bandgap filters, ADCs and DACs.
The new 50V smart power technology is built around the AMIS low-voltage (LV) 0.35um CMOS semiconductor process that features metal-metal capacitors and well matched high-ohmic resistors.
As with the 80V I3T80 technology announced in September 2002, I3T50 is available with a full library of high-voltage DMOS and bipolar devices including high-performance floating vertical nDMOS transistors.
These transistors have a drain-to-source on resistance below 50mohm/mm2 at a breakdown voltage in excess of 50V.
Electrostatic discharge (ESD) capability for the I3T technology is rated at 4.5kV HBM (human body model) and 750V CDM (charge device model).
In addition to ARM7TDMI and 8051 embedded processor cores, a comprehensive family of IP blocks that simplify and speed the implementation of I3T50 smart power SoCs is available.
These blocks include PLLs, USB interfaces, bus protocol controllers, and controllers for CAN and LIN connectivity.
A wide variety of memory options including ROM and RAM macros are available, while high-density Flash solutions will also be developed.
Commenting on the launch of the new I3T50 technology, Marnix Tack, Director Technology at AMI Semiconductor, states: "I3T50 allows developers to rapidly implement smart power solutions that combine digital, analogue and high-voltage circuitry into a single, compact smart power IC.
As a result, I3T50 is an excellent vehicle with which to design compact and robust SoCs that save space, reduce component count and minimise both cost and time-to-market".
The first working I3T50-based prototypes have already been produced and successfully evaluated in a target application.
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