Product category:
Communications ICs (Wireless)
News Release from: Analog Devices | Subject: AD6633 and AD6636
Edited by the Electronicstalk Editorial
Team on 23 March 2004
Up-convertor cuts basestation power
budget
The AD6633 is a digital up-convertor featuring breakthrough technology claimed to significantly reduce output power requirements for 3G wireless basestation power amplifiers.
The AD6633 is a digital up-convertor featuring breakthrough technology claimed to significantly reduce output power requirements for 3G wireless basestation power amplifiers The AD6633's innovative VersaCrest crest reduction engine enables optimum baseband-to-IF (intermediate frequency) signal conversion by anticipating and reducing power peaks earlier in the signal chain
This article was originally published on Electronicstalk on 14 Sep 2001 at 8.00am (UK)
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The AD6633 is Analog Devices' first digital up-convertor with crest factor reduction technology for cdma2000, W-CDMA and TD-SCDMA 3G wireless transmitter applications.
Operating at 125Msample/s and processing four or six channels, the AD6633 is capable of trading crest factor reduction against signal distortion.
The signal distortions can be allocated dynamically to any individual channel; thus allowing operators to configure performance preferences for high quality data or lower quality voice communications.
The convertor also features programmable wideband channel filters that can be implemented for cdma2000, W-CDMA or TD-SCDMA standards, enabling manufacturers to use a single device across multiple platforms.
"As demand for 3G services accelerates, wireless infrastructure manufacturers and assembly contractors will be seeking effective design solutions that reduce their starting capital and operational costs", said Kevin Kattmann, Product Line Director for High-Speed Convertors, Analog Devices.
"The AD6633's innovative VersaCrest crest-reduction engine delivers unparalleled signal conditioning performance in peak-to-average power reduction and reduces the power amplifier cost component within base station designs - a winning combination for both our customers and their subscribers".
The AD6633 wideband transmit signal processor operates on up to six-channels with user configurability and speeds of 125Msample/s.
Its VersaCrest crest reduction engine reduces demands on external power amplifiers.
It features one 20bit input port, shared among six processing channels, with 18bit parallel output ports.
Filters include: all-pass phase equaliser filters for cdma2000, programmable RAM coefficient FIR filters with resampling, FIR interpolating filters (two per channel), complex FIR filters with frequency equalisation and fifth-order interpolating CIC filters (one per channel).
It offers full complex NCO for 32bit tuning fine resolution, worst spur better than -105dBc, and output automatic gain control.
The AD6633 requires 3.3V input/output and 1.8V core supplies.
In addition to 3G wireless infrastructure applications, the AD6633 is also suitable for general-purpose communications applications where power crests and system costs present design challenges.
Analog Devices also has a new wideband digital down-convertor for multicarrier receivers.
The AD6636 wideband digital down-convertor is capable of processing up to six UMTS, cdma2000 or TD/SCDMA channels at speeds up to 150Msample/s.
Each channel is dynamically reconfigurable, operates independently, and includes cascaded signal-processing elements: a frequency translator, programmable decimating filter, and automatic gain control (AGC) circuitry that optimises the dynamic range of the system.
The receiver input block allows routing of the ADC data to any or all of the six receive processing channels.
The AD6636 features a fractional clock multiplier that uses the ADC clock to produce a digital down convertor master clock up to 200MHz.
This internal phased-locked loop (PLL) allows optimum digital clock rates, regardless of the convertor sampling rate, enabling the best possible digital signal decimation and filtering.
Two 16bit parallel output ports accommodate high data rate 3G applications.
An on-chip interpolating half-band filter can also be used to further increase the output rate while still allowing for very efficient filters.
In addition, each parallel output port has a digital AGC for output data scaling.
The AD6633 up converts baseband data from the digital signal processor (DSP) to a digital IF.
This coupled with Analog Devices AD9777 TxDAC+, and AD8349 direct RF up-convertor offers a complete, highly programmable transmit signal chain.
On the receive side this is complemented by the AD8343 high IP3 active mixer and the AD6654 MxFE wideband IF-to-baseband convertor.
Rounding out this complete signal chain portfolio for wireless infrastructure is the high-performance TigerSHARC processor.
Achieving 4.8 billion multiply accumulates per second (GMACS) and 3.6 billion floating-point operations per second (GFLOPS) at 600MHz, the TigerSHARC ADSP-TS201 can support full software radio implementations in 3G wireless basestations.
The AD6633 and AD6636 are sampling now and will be available in production quantities in August 2004.
They are available in 196-lead BGA (ball grid array) packages.
The AD6633 is priced at $60.00 per unit in 10,000-piece quantities for the six-channel version and at $40.00 per unit in 10,000-piece quantities for the four-channel version.
The AD6636 is priced at $43.50 per unit in 10,000-piece quantities for the six-channel version and at $29.00 per unit in 10,000-piece quantities for the four-channel version.
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