Product category:
Communications ICs (Wired)
News Release from: Analog Devices | Subject: ADN2865
Edited by the Electronicstalk Editorial
Team on 10 March 2006
Serdes is optimised for passive optical
networks
A new serialiser-deserialiser is designed to address the specific performance, power and price requirements of passive optical networking terminals.
Analog Devices is introducing a serialiser-deserialiser (serdes) designed to address the specific performance, power and price requirements of passive optical networking (PON) terminals The ADN2865 is the industry's first serdes to use a loop-timed architecture optimised for PON optical network terminals (ONTs), enabling the device to offer significant advantages-such as low power, reduced cost and fixed latency-as compared with existing serdes solutions
This article was originally published on Electronicstalk on 2 Jul 2008 at 8.00am (UK)
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This architecture also allows the ADN2865 to deliver the industry's widest performance margin beyond Sonet specifications, thus easing interoperability issues and improving system performance.
The ADN2865 serdes utilises ADI's patented dual-loop clock and data recovery (CDR) architecture to provide jitter performance that exceeds the Sonet specifications by a factor of three in all categories (jitter generation, jitter tolerance, jitter transfer.) The device supports all datarates for gigabit PON (GPON), Ethernet PON (EPON) and broadband PON (BPON) and is designed to seamlessly integrate with the least-expensive FPGAs from leading vendors.
The ADN2865 is the first serdes to offer fixed latency, a necessary feature that allows system vendors to maximise throughput and control over their PON systems.
In addition, the ADN2865 offers low power consumption of less than 1W and features an optional bypassable limiting amplifier.
The ADN2865 serdes is available in production quantities now and is packaged in an 8 x 8mm LFCSP (lead frame chip scale package).
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