Product category:
Design and Development Software
News Release from: ARM
Edited by the Electronicstalk Editorial
Team on 20 February 2004
Cores to gain help with system-level
verification
Verisity and ARM are working to provide mutual customers with verification IP solutions that address the ever-growing complexities of system-level verification.
Verisity and ARM are working to provide mutual customers with verification IP solutions that address the ever-growing complexities of system-level verification The two companies will jointly develop verification IP for the ARM11 core family
This article was originally published on Electronicstalk on 8 Nov 2004 at 8.00am (UK)
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Starting with the AXI e Verification Component (eVC), and advanced methodologies based on Verisity's VPA solutions.
Many of the ARM semiconductor partners are pushing the limit of system integration on a single chip.
These designs, many of which are based on the ARM11 microarchitecture require billions of verification cycles and hundreds of Gbytes of information, distributed over several compute and engineering resource locations.
It is with this problem in mind that ARM has teamed up with Verisity to help ease the issues associated with the verification of these next-generation designs.
"We believe that the next generation of chip developments need an automated verification process that spans the block, system, and project levels", said Alan Hunter, Verification Methodology Manager, ARM.
"The VPA solutions offered by Verisity, work well with a new set of verification IP components, under development, and enable our customers to run ARM verification suites out-of-the-box.
This will make the verification of ARM core-based design quicker and easier in the future".
The ARM11 processor family comprises a range of high-performance microprocessor cores and platforms that exploit the new high-data throughput Amba 3.0 AXI bus system.
The AXI eVC will be part of a complete verification environment for the AXI bus, including block and chip level scenario generation, data and assertion checking and specification based functional coverage analysis.
The AXI eVC will comply with Verisity's e Reuse Methodology (eRM) and will run AXI verification scenarios, supplied by ARM.
"Solving the challenges of system-level verification requires automated processes leveraging reuseable, adaptable verification environments", said Steve Glaser, vice president of corporate marketing and business development for Verisity.
"The verification IP ARM and Verisity are jointly developing will enable the highest productivity and scalability, while supporting a spec-driven verification flow all the way through closure".
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