Product category:
Design and Development Software
News Release from: ARM | Subject: Cadence SI views
Edited by the Electronicstalk Editorial
Team on 29 October 2004
Signal integrity views aid SoC
integration
Cadence Design Systems and ARM can now supply signal integrity (SI) views from ARM for Foundry Programme partners.
Cadence Design Systems and ARM can now supply signal integrity (SI) views from ARM for Foundry Programme partners For designers incorporating hardened ARM processors into their designs, these views give access to critical data required to perform detailed voltage drop and SI analysis
This article was originally published on Electronicstalk on 8 Nov 2004 at 8.00am (UK)
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This analysis speeds time-to-market of nanometre-scale system-on-chip (SoC) designs by rapid detection and resolution of critical SI issues.
The ARM processor views support industry-leading Cadence tools, including CeltIC crosstalk analysis and repair and VoltageStorm power grid analysis, which are core technologies within the Cadence Encounter digital IC design platform.
As customers move to 130nm and below, voltage drop and SI issues pose increased risks of chip failure and poor yield.
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When combined with the growing use of hardened intellectual property (IP), the risk of critical design problems due to SI issues is even greater because designers previously had no SI views for the hardened IP.
This joint solution provides the critical characteristics of hardened IP processors provided by ARM that will enable designers to find and correct SI problems earlier in the design process, speeding time to market for ARM partners.
"The collaboration between Cadence and ARM to deliver these views will enable us to identify and correct potential chip failure and yield loss problems before tapeout, and shorten our time-to-market", said Dr Chi-Sin Wang, Chairman and Chief Executive Officer at Centrality Communications.
"The availability of these models will enable us to fully utilise the capabilities of Cadence's SI analysis solutions in our SoC designs".
"ARM and Cadence have provided yet another important capability to enable faster, and more accurate verification of designs incorporating hardened ARM IP", said Keith Clarke, Vice President, Engineering, ARM.
"The codevelopment of these SI views further reduces the risk for our Foundry Programme partners, and will continue to help reduce overall time to working silicon for our partners".
"Identifying and correcting signal integrity issues early in the design cycle is critical to first silicon success", said Jan Willis, Senior Vice President, Industry Marketing, Cadence.
"By optimising the silicon design chain for our customers, Cadence and ARM are enhancing the successful implementation of nanometre designs".
The signal integrity views are available from ARM for its Foundry Programme partners.
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