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Product category: Design and Development Software
News Release from: ARM | Subject: RealView ESL
Edited by the Electronicstalk Editorial Team on 08 March 2005

System-level design tools speed
prototyping

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RealView ESL tools are now available to support ARM11 family-based system prototyping.

RealView ESL tools are now available to support ARM11 family-based system prototyping The RealView ESL tools reduce and improve the full design process by working at the cycle- and transaction-based abstraction level to enable a complete virtual platform for modelling and programming multicore SoCs before silicon production - leading to faster time to market

Published reports state that virtual prototyping reduces system silicon design for applications like HD digital TVs, 3G mobile phones, mobile application processors and other complex devices by up to 40%.

The ARM RealView ESL tools incorporate MaxSim technology, which assists software and hardware design teams by enabling architecture exploration and software development to begin before the silicon or RTL of the final product are available.

Benchmarking and tradeoff analysis is conducted in a readily available environment offering bus, cache and software profiling and analysis functions.

High simulation speed, comprehensive software control and visualisation enable early identification and removal of software errors.

The RealView Model Library, which incorporates MaxLib SystemC models, includes cycle accurate models of all ARM11 family uniprocessors, as well as models of other configurable system components which use the Amba 3 AXI interconnect protocol: the ARM PrimeCell Amba 3 configurable interconnect (PL300), the PrimeCell dynamic memory controller (PL340), and the PrimeCell level 2 cache controller (L220), as well as a complete set of bridge components enabling the easy connection of existing peripherals and bus models which use Amba 3 protocols.

"ARM11 family processors continue to gain momentum in the marketplace; first introduced in 2002, they have been licensed by more than 25 ARM partners and have an established, and very well-understood implementation flow", said Noel Hurley, CPU Product Marketing Manager at ARM.

"With the introduction of our new RealView ESL tools, we are able to provide developers with an end-to-end ARM11 system solution, which will reduce system design time and costs for current and future ARM11 processor-based design activity".

The ARM1176JZ(F)-S processor is a member of the ARM11 family which also includes the ARM1136J(F)-S processor, the ARM1156T2(F)-S processor, and the scalable single- to four-core ARM11 MPCore multiprocessor.

The cores in the ARM11 family can achieve 550MHz in TSMC 0.13um technology and depending on configuration, use as little as 2.2mm2 of silicon area and 0.45mW/MHz of power.

All ARM11 family processors include Thumb instructions for code compression.

The ARM1156T2(F)-S processor includes the Thumb-2 instruction set that provides further improved performance and code compression.

The ARM1176JZ(F)-S processor also incorporates Jazelle technology for Java acceleration and critical new technologies such as TrustZone technology for security and Intelligent Energy Manager (IEM) technology for increased power savings.

It was also the first processor to use the Amba 3 AXI protocol high-bandwidth system interface.

Both the ARM1156T2(F)-S processor and the ARM11 MPCore multiprocessor also use the Amba 3 AXI protocol.

The ARM1176JZ(F)-S PrimeXsys Platform extends the TrustZone and IEM technology benefits into the rest of the system and provides a high-performance, configurable platform including high-speed interconnect, an optimised DDR-SDRAM controller and level-2 cache control.

In addition to IEM energy management technology, the ARM1176JZF-S processor and the ARM1176JZ-S processor, in common with all IEM technology enabled processors, can be implemented with the low power features of the ARM Artisan Metro platform.

The Artisan Metro low-power platform provides physical IP specifically designed to significantly reduce power while lowering costs through increased density and yield.

The Metro platform incorporates new architectures, circuit designs and low-power features enabling IC designers to implement dynamic voltage scaling and other advanced chip-level power management techniques.

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