Product category:
Intellectual Property Cores
News Release from: ARM
Edited by the Electronicstalk Editorial
Team on 15 June 2005
IBM to use IP library for 65nm ASICs
ARM Artisan Metro low-power standard cell libraries, memory compilers and I/Os have been selected for IBM's newest 65nm application-specific integrated circuit product offering.
ARM Artisan Metro low-power standard cell libraries, memory compilers and I/Os have been selected for IBM's newest 65nm application-specific integrated circuit product offering Collaborating with a third-party library provider like ARM is in line with IBM's common platform design strategy and an important component of its first comprehensive low-power ASIC offering for the high-volume wireless, mobile and consumer electronic markets
This article was originally published on Electronicstalk on 7 Jun 2005 at 8.00am (UK)
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"ARM welcomes the opportunity to collaborate with IBM and combining the expertise of both companies will result in innovative low-power solutions for current and future leading-edge consumer applications", said Neal Carney, Vice President of Marketing, Physical IP, ARM.
"ARM's expertise in low-power design and proven track record of delivering quality physical IP to IBM were critical factors in being selected for IBM's first comprehensive low-power ASIC offering and we look forward to continuing the collaboration for future offerings".
"By collaborating closely with ARM on the new ASIC offering and leveraging ARM Artisan libraries IBM will be well positioned to service the ASIC needs of the fast-growing consumer marketplace", said Tom Reeves, OEM Vice President, Semiconductor Products for IBM Systems and Technology Group.
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The agreement between ARM and IBM is an expansion of the companies' collaborative efforts announced earlier this month where ARM Artisan Metro products are now a part of the 65nm Common Design Platform for foundry customers of both IBM and Chartered.
The physical IP product available on IBM's 65nm low-power process incorporates the combined expertise of IBM and ARM in addressing the complexities of leading-edge technologies, power management and design for manufacturability.
This same set of low-power ARM IP is the technology foundation on which IBM's new low power ASIC offering (Cu-65LP) is built.
The IBM Cu-65LP has been created on proven, industry-standard ARM Artisan physical IP libraries and is coupled with IBM's ASIC methodology to enable fast design closure and first pass success designs.
IBM has adopted ARM Artisan IP in support of its foundry customers across multiple generations of technology including 180, 130, 90 and 65nm nodes.
With this announcement, IBM has extended the use of ARM Artisan IP in to the ASIC side of its business.
The Artisan Metro IP at 65nm will support foundry customers on commercial EDA design flows while IBM build its ASIC methodology on top of this common, industry standard IP.
This approach to design and industry collaboration provides clear business benefits to IBM and preserves the key value proposition and differentiation of its ASIC offering.
Specifics of the ARM-based IBM ASIC product were detailed this week at the 2005 Design Automation Conference (DAC) in Anaheim, California.
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