Product category:
Intellectual Property Cores
News Release from: ARM | Subject: EmBISTRx
Edited by the Electronicstalk Editorial
Team on 25 October 2006
Memory compilers integrate test and
repair
Embedded memory test and repair system is tightly integrated with the ARM Advantage and Metro memory compilers.
ARM has announced the availability of its new advanced emBISTRx embedded memory test and repair system that is tightly integrated with the ARM Advantage and Metro memory compilers, part of its family of Artisan physical IP The ARM fully embedded memory subsystem with integrated built-in-self-test (BIST) and built-in-self repair (BISR) IP increases overall chip yield to reduce chip cost, raise profit margins and enhance manufacturing test quality for Advantage and Metro memories for 45, 65 and 90nm processes
This article was originally published on Electronicstalk on 8 Nov 2004 at 8.00am (UK)
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As memory content increases to thousands of individual memory instances in nanometre designs, system-on-chip (SoC) designers are challenged on multiple fronts, in managing the impact on design parameters such as power, performance and area.
Additional areas of impact are development productivity, ensuring repairability for yield enhancement and high-test quality.
Unlike existing approaches where different controller types are required for different types of memory, the advanced ARM emBISTRx system is based on a hierarchically distributed architecture.
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With the ARM solution, a centralised shared BIST/BISR controller manages many different sizes and types of register files and memories with smart wrappers designed to be placed close to the memory instance.
The benefit of ARM's integrated approach is that it minimises the area impact on the overall memory subsystem through optimal partitioning of the test and repair logic between the controller, wrapper and memory macro.
Depending on the design and implementation, average area reduction in the range of 20-30% can be observed as compared with conventional approaches.
Additionally, the ARM emBISTRx solution reduces the number of interconnects and routing congestion, which results in area savings and faster timing closure.
This area efficient, architectural approach allows designers to optimise timing-critical paths and enables at-speed testing, a critical requirement for many high-speed consumer and enterprise applications.
To enhance design productivity, the ARM emBISTRx system includes an automation tool to insert and stitch the BIST/BISR logic into the design, which reduces implementation time and eliminates design errors.
The ARM emBISTRx system is tightly integrated with the ARM memory compilers to offer designers an easy-to-use solution for implementing the ARM embedded memory subsystem.
In addition to the traditional approach of targeting standard memory fault types, the ARM emBISTRx system includes algorithms that detect real world silicon defects in nanometre technology such as excessive leakage, weak bits, and subtle behaviour such as resistive shorts and opens that can result in low yield.
The defect-based BIST algorithms are architected to minimise test escapes, which can potentially save millions of dollars in cost for high-volume products.
The ARM emBISTRx system is tuned to ARM's specific memory redundancy architecture, which is based on memory defect data, bit-cell yields and related foundry recommendations.
"As our customers move from 90nm to 45nm and beyond, they are facing many challenges to deliver higher yielding memories with robust test quality, and at the same time satisfy the area and timing constraints", said Neal Carney, Vice President of Marketing, Physical IP, ARM.
"With the introduction of the ARM emBISTRx solution, we are delivering an area-optimised embedded memory subsystem tightly integrated with test and repair capability to enable our customers to meet their overall yield goals with high-test quality and higher profit margins".
"This solution simplifies the challenge of adding test and repair into complex SoCs enabling our customers to get to market quickly".
The ARM emBISTRx product will be available in Q4 2006 and pricing will be based on customers' selection of memories and process technologies.
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