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Product category: Design and Development Software
News Release from: Apache Design Solutions | Subject: RedHawk-ALP
Edited by the Electronicstalk Editorial Team on 17 April 2007

Power-saving software evolves for new
processes

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Physical power integrity solution for advanced low power and leakage control designs targets power savings and leakage control techniques used in 65/45nm devices.

New from Apache Design Solutions, RedHawk-ALP is a physical power integrity solution for advanced low power and leakage control designs RedHawk-ALP targets power savings and leakage control techniques used in 65/45nm designs including: VTCMOS (variable threshold CMOS) circuits with substrate back-biasing; power-gated memories and custom macros; and on-chip LDO voltage regulators

Apache led the market in delivering the first dynamic solution, RedHawk-LP, for MTCMOS (multiple threshold CMOS) ramp-up and rush current analyses, power switch optimisations and full-chip mixed-mode verification.

As designs move towards 45nm, designers are faced with new challenges which require even more aggressive techniques to reduce leakage.

With RedHawk-ALP, Apache extends its low power leadership position to be the first in the market to provide a comprehensive solution that addresses these advanced techniques.

VTCMOS is a new circuit technique for reducing the leakage current by dynamically altering the substrate voltage.

However, varying of the substrate voltage introduces noise on the supply source and increases variability in circuit behaviour.

Apache's RedHawk-ALP accurately extracts bias networks and analyses full-chip dynamic power integrity including instance-based threshold voltage and current for design tradeoff analysis.

MTCMOS, or power-gating, has been widely used for reducing leakage by controlling the on/off switching of logic blocks or cells in 90/65nm designs.

As designs move towards 45nm, designers must add power switches to memories and custom IP to further reduce leakage.

RedHawk-ALP expands modelling capabilities and simulation capacity of the existing cell-/block-level MTCMOS support to handle large GDS-based custom macros.

On-chip LDOs are often used to deliver the desired voltages to different parts of the chip (voltage islands) without introducing extra power pins.

As an LDO is an analogue circuit with a continuous output voltage waveform, designers traditionally had to use Spice to simulate its behaviour.

At the full-chip level, LDO was typically modelled by an ideal voltage source, which hides the potential power noise generated by the LDO circuit.

Apache's RedHawk-ALP accurately models LDO circuit and provides the true transient behaviour for full-chip power noise analysis.

"Apache continues to lead the market in addressing the critical design needs as we move toward 65 and 45nm processes", said Dian Yang, Vice President of Product Management at Apache.

"Our new product enables IC designers to better understand the behaviour of advanced low power techniques and to allow designers to make effective leakage versus performance tradeoff decisions".

"RedHawk-ALP is Apache's continued commitment to expand our solutions for critical silicon integrity signoff".

RedHawk-ALP is available as beta now and will be available for production use in Q3, 2007.

An annual licensing start at US $330,000 list and is upgradeable from existing RedHawk-LP licence.

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