Product category:
Design and Development Hardware
News Release from: ARC International | Subject: ScanICE-ARC and NetICE-ARC emulators
Edited by the Electronicstalk Editorial
Team on 20 February 2001
ARC emulators use JTAG to cut external
hardware
Available from ARC Cores are the first JTAG emulators for a configurable processor to provide powerful development and test capabilities normally only available with external hardware.
Available from ARC Cores are the first JTAG emulators for a configurable processor that provide powerful development and test capabilities normally only provided by bulky and expensive external hardware The two new emulators from Corelis make use of ARC's unique on-chip debug capabilities to provide features that support any processor clock speed at which the target system runs, and are capable of supporting future processors from ARC
This article was originally published on Electronicstalk on 6 Jun 2001 at 8.00am (UK)
Related stories
Board supports soft-processor-based SoC designs
ARCangel 3 from ARC Cores is a new development platform supporting the latest available FPGAs.
Integrated development package for Bluetooth SoCs
BlueForm from ARC Cores is a comprehensive package of hardware and software IP, development tools and application software for building Bluetooth SoC products based on the ARCtangent processor.
The new ScanICE-ARC and the NetICE-ARC emulators from Corelis use the standard JTAG port on ARC's Tangent processor to provide access to its on-chip debug facilities.
Both emulators include the powerful MetaWare Windows 95/98/NT/2000 compatible SeeCode source-level debugger.
For JTAG emulation access, the ScanICE-ARC uses a PCI bus JTAG controller that is installed in a PC, and the NetICE-ARC uses a LAN-based (Ethernet) JTAG controller.
Further reading
Novel architecture mixes 16 and 32bit instructions
ARCompact is an innovative instruction set architecture (ISA) from ARC Cores that allows designers to mix 16 and 32bit instructions on its 32bit user-configurable processor.
IP runs on ARC core to provide futureproof audio
Fraunhofer IIS has developed the first IP solution for audio applications such as MP3 and AAC from a single source that is foundry independent and can be adapted for future audio standards.
ARC's on-chip debug capabilities are unique in the embedded market place, and provide three main advantages to the system developer - nonintrusive memory access, no debug firmware required and multicore debug.
To support real-time debugging, the on-chip logic enables users to examine memory locations without stopping the processor.
Debug operations can be achieved with no resident code running on the CPU, resulting in zero memory overhead for full system debug.
In the case where an SoC design uses multiple ARC cores, the ARC Tangent processor provides a mechanism to multiplex a single debug link over multiple processor instantiations, minimising the number of pins required for debugging.
Unlike conventional real-time emulators that rely on bulky and expensive external hardware pods, the Corelis emulators use the JTAG standard test access port to access the internal debug resources available on ARC's Tangent processor.
This eliminates the need for external pods, thus reducing the cost and electrical loading of the target system.
As the debug resources used by the emulator are integrated on the target processor, the emulator automatically supports any clock speed at which the target system runs.
In addition to these benefits, the use of the JTAG interface also ensures that processor access is maintained even when the user's software 'hangs' or otherwise runs out of control.
Programs and data can be downloaded to any part of the system RAM through the JTAG port without the need for a resident loader program or a ROM emulator.
The standard four-wire JTAG interface allows it to be connected to ARC's processor, and any future processor developed by ARC.
Thus, switching processors from one design to the next does not obsolete a user's investment in their emulator hardware.
As an additional benefit, each of the JTAG controllers, can be used to provide boundary-scan interconnect testing and in-system programming (ISP) of Flash devices and CPLDs using Corelis ScanPlus optional boundary-scan test and ISP software.
• ARC International: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
