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Intellectual Property Cores
News Release from: ARC International | Subject: Real-time trace
Edited by the Electronicstalk Editorial
Team on 07 November 2001
Real-time trace aids 32bit debug
ARC Cores has introduced a real-time trace solution for the industry-leading ARCtangent-A4 user-customisable 32bit processor.
ARC Cores has introduced a real-time trace solution for the industry-leading ARCtangent-A4 user-customisable 32bit processor, enabling SoC debugging at a system's target operating frequency without major silicon or pin-count overheads Designers can now get full visibility into a chip, even for multiple processor systems, enabling full high-performance real-time debugging of a product development or design
This article was originally published on Electronicstalk on 20 Feb 2001 at 8.00am (UK)
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Historically, one of the biggest barriers in implementing real-time trace debug capability has been the penalty paid in silicon real estate and pins for the host interface.
Even as process geometries decrease, reducing the overall area requirement of a real-time trace (RTT) system, the relative size of an acquisition, store and transmit system for real time tracing remains large in comparison to core sizes.
But for some chip developers visibility inside the chip is vitally important, to analyse and trace the history of instruction execution profiles, data transactions, and system events inside the processor.
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RTT is the only mechanism capable of providing this level of information on real silicon, executing in real time.
Developed in response to customer requirements, ARC's solution is a low pin-count real time trace system offering high compression rates, and offers significant information output and filtering.
Together with multiple ARCtangent processor support and high throughput transfer rates, the ARC solution is unrivalled by other RTT solutions currently available for embedded 32bit RISC processors.
The ARCtangent RTT is fully supported by the ARChitect point-and-click graphical-user-interface tool, and the MetaWare SeeCode debugger features full support for trace import and analysis (including disassembly back to C/C++ level).
Advanced features such as stepping through the trace history are supported by the debugger.
Host systems can gather the trace information using a logic analyser, with information generated being parsed and displayed by the debugger.
Trace events that can be analysed using ARC's Real-Time Trace include: instruction trace; data trace; timing trace; external events; user events; actionpoint events; and interrupts.
ARC's trace system runs independently of the rest of the system, allowing the developer to start, stop, and examine the trace data without slowing the code at all - so if the processor is running at 200MHz, ARC's trace facility allows this to continue running while it is being analysed.
The system uses a combination of static and dynamic trace ports for information exchange between the microprocessor and the RTT display.
The compression techniques used by ARC for the trace debug feature include variable length encoding, delta-encoding of addresses, run-length encoding and instruction set specific optimisations, enabling full instruction trace of three ARCtangent cores using a single 4bit interface.
The real time trace unit, like all ARC's core IP, is configurable which allows customers to select the level of information, triggering and buffering to be supported - optimising the gate count of the RTT system to the needs of the SoC designer - in addition to the number of pins required by the user (4 to 32bit interfaces supported).
The real-time trace facility will be available from ARC Cores as an integrated optional addition for the ARCtangent processor at the end of Q1 2002.
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