Synopsys tools join the ARC design flow

ARC International has made two important new technology developments in integrating Synopsys' tools into its design flow.

ARC International has made two important new technology developments in integrating Synopsys' tools into its design flow.

The collaboration between Synopsys and ARC speeds development and verification of SoC devices, enabling much faster time-to-volume production for ARCtangent processor-based designs.

The first technology development addresses a key SoC verification challenge for configurable intellectual property (IP), ensuring that the soft IP generated by the ARChitect processor-builder tool is verified to function correctly when designers use different system configurations.

Using Synopsys' Vera test bench automation tool suite, ARC's customers now have access to a high-level system verification environment to test both the processor and multiple peripherals such as USB1.1, USB 2.0 and Ethernet MAC integrated into a SoC.

This solution, which is unique for a configurable processor, facilitates the verification of the complete SoC - including processor and peripherals - by providing directed random assembler test code and random peripheral data traffic simultaneously to find difficult corner cases.

VERA brings complete control to the instruction stream and peripheral data traffic, which is key to finding the most difficult design bugs.

All System-Level transactions are monitored to ensure correct operation while Functional Coverage statistics are gathered.

This Verification IP is supplied to ARC's customers using the Vera Core delivery mechanism, enabling the System Level Verification environment for the ARC IP to be re-used for verification of the customer's complete SoC.

The second technology development, known as RTL performance prototyping (RPP), has been introduced as a new capability in Synopsys' Physical Compiler.

RPP provides designers with a well-documented and predictable route to silicon, which becomes an important issue particularly for leading-edge technologies at 0.18 micron and below.

ARC will provide its customers with integrated support within its design flow for Synopsys' Physical Compiler and Chip Architect.

ARC will also extend this support to encompass DFT Compiler for scan insertion, Power Compiler for low power optimisation, and PrimeTime and Formality for static timing analysis and formal proof of the equivalence of the RTL to the placed-gates netlist.

This greatly eases the implementation flow from the RTL generated by ARC's processor configuration tool, ARChitect, to placed gates - thereby improving the predictability and accuracy of the final results.

"ARC believes in providing the best tools for the job to help our customers get their products designed and into volume production fast", said Haig Yaghoobian, senior vice-president, corporate development, for ARC International.

"Our industry-leading user-customisable 32bit RISC/DSP processor, software, hardware and development tools, together with EDA technology from an industry leader like Synopsys, will help us to meet that challenge".

"By working closely with Synopsys, ARC is able to speed the adoption of its processor and related technology into customer designs", said Sandeep Khanna, senior director of marketing for physical synthesis from Synopsys.

"With Physical Synthesis, designers using the ARCtangent processor will be able to compile the ARCtangent processor and close timing quickly.

Additionally, use of Vera test bench automation product ensures correct integration of ARCtangent into an SoC design by reuse of Vera verification environment that monitors correct operation of the configurable IP".

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