Product category:
Intellectual Property Cores
News Release from: ARC International | Subject: USB-HS SPH and USB-HS MPH
Edited by the Electronicstalk Editorial
Team on 02 October 2003
IP embeds High-Speed USB host
controllers
ARC International has a new family of single- and multiport USB High-Speed (USB-HS) host controllers.
ARC International has a new family of single- and multiport USB High-Speed (USB-HS) host controllers The new host-specific solutions are highly optimised, low-gate-count IP cores that allow system designers to develop compact, cost-effective USB SoCs
This article was originally published on Electronicstalk on 20 Feb 2001 at 8.00am (UK)
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The ARC USB-HS single-port host (SPH) core delivers the industry's lowest gate count for a single-port USB-HS host controller, and the ARC USB-HS multiport host (MPH) core is the industry's first MPH controller solution for embedded USB-HS applications.
Each controller port is backward compatible and is able to operate individually at high speed, full speed or low speed.
This function is critical as a large number of USB applications are in the process of migrating from exclusively USB full speed to a combination of full- and high-speed ports.
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The new family of host controllers is targeted for set-top boxes, high-end video gaming systems, residential gateway devices and printer applications for "PC-less printing".
"Our experience in the USB market, coupled with our overall embedded system knowledge, enables us to deliver low-risk solutions to our customers that help them get to market fast", said Mike Gulett, ARC's President and CEO.
"In developing our new family of single- and multiport USB-HS host controllers, we utilised our USB experience to provide our customers with a highly optimised IP core, enabling them to implement compact, cost-effective USB-based SoC solutions.
We believe this family of host controllers will allow us to extend our leadership position within the USB IP market".
As system architectures vary widely, the new USB host-specific controllers were developed to be highly configurable and programmable, making the cores an excellent match for all system architectures, regardless of their system bus characteristics.
Programmable features under software control include adaptive tuning, programmable fill level and enhanced streaming.
The single-port, host-specific controller is offered as either VHDL or Verilog source code and is capable of operating at all three existing USB speeds.
The core is EHCI-compatible and supports both UTMI+ and ULPI PHY interfaces.
Designed for high performance and low cost, the core integrates a protocol-aware DMA engine that provides maximised USB data throughput.
The controller's advanced latency buffer architecture eliminates the need for dedicated FIFOs, reducing the number of bus cycles required to accomplish transfers by more than half compared with alternative dedicated FIFO approaches.
This reduction in bus cycles translates directly to a reduction in power consumption and also frees up the system processor for other tasks.
The need to design a DMA controller is also eliminated.
ARC's USB-HS MPH controller is EHCI-compatible and supports the UTMI+ interface now and will support ULPI PHY interface as it becomes available.
The controller delivers two to eight ports, which can individually operate at high-speed, full-speed or low-speed, while maintaining all the architectural advantages of the single-port solution.
An integrated transaction translator enables all high-speed ports to share a combined bandwidth of 480Mbyte/s.
All full-speed ports can share a combined bandwidth of 12Mbyte/s.
Both the single-port and multiport product use proven host functionality, delivered as a component within the ARC USB-HS On-The-Go product.
The ARC host's data throughput has been measured in ARC labs, under real-world conditions, and has been found to be on a par with larger, "chipset" implementations found on PC motherboards.
Specific throughput measurement methodology and results are available via ARC sales channels.
ARC's SPH and MPH High-Speed USB products are supplied as synthesisable, technology-independent VHDL or Verilog RTL source code.
As part of its total USB solution, ARC provides customers with simulation test benches and synthesis scripts, as well as proven USB software stacks, class and device drivers.
Additionally, through ARC's CertiPHY programme, ARC delivers its customers with a proven portfolio of PHYs and PHY macrocells that interoperate with ARC USB controllers.
The USB-HS SPH controller is available now.
The USB-HS MPH controller will begin shipping in Q4.
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