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News Release from: ARC International | Subject: ARC 600
Edited by the Electronicstalk Editorial
Team on 16 October 2003
Configurable processor optimises speed
and power
The new ARC 600 architecture is claimed as the industry's smallest and lowest power RISC/DSP-based 32bit configurable processor.
The new ARC 600 architecture is claimed as the industry's smallest and lowest power RISC/DSP-based 32bit configurable processor The architecture offers designers high-speed operation, low power and enhanced DSP functionality in a small footprint
This article was originally published on Electronicstalk on 1 Jul 2004 at 8.00am (UK)
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RISC/DSP core upgrades media centre chipset
Digeo has licensed the ARC 600 RISC/DSP core, MetaWare development tools, and MP-3 and AC-3 audio technology for use in its X-Stream media centre chipset.
Processor cores gain RTOS support
ARC International has collaborated with Express Logic to provide ThreadX RTOS support for the ARC 600 and ARC 700 configurable processor cores, as well as the ARCtangent cores.
In its base-case RISC-only configuration, the ARC 600 architecture core is 50 to 85% smaller than processors in its class and consumes up to 50% less power.
With the ARC 600's configurability and extendibility, designers have the necessary tools to balance the processor's speed, area, and power to develop an optimal solution for their specific application.
The ARC 600 architecture features sophisticated power management schemes that include fine clock gating and I-cache way prediction.
Further reading
Configurable core gains reference methodology
Magma Design Automation and ARC International have developed a validated reference methodology for the ARC 600 configurable microprocessor core.
Configurable cores aim for high-growth markets
The ARC 600 and 700 families now include eleven configurable cores that enable developers to meet specific requirements of high-growth embedded markets.
Core extensions ease debug tasks
ARC International has added new configurable trace and debug extensions to its ARC 600 and 700 core families.
By implementing a clock gating methodology that fits into existing design flows and not clocking registers when they are not switching, the ARC 600 significantly lowers the core's power.
Further saving system power, the architecture's I-cache way prediction eliminates unnecessary accesses to memory by looking at tag information in the previous clock cycle to access only a single data RAM on a cache hit.
Addressing the impact of program memory on system cost, the ARC 600 RISC/DSP architecture also features the ARCompact instruction set architecture.
The 16/32bit ISA reduces code size by 30% or more when compared with standard 32bit-only ISA architectures, enabling customers to implement a lower cost and lower power solution.
As part of the ARC 600's extendibility, designers are able to include their own customised instructions or predefined ARC DSP instructions to further reduce code size and frequency requirements.
With its five-stage pipeline and extendible RISC/DSP architecture, the ARC 600 offers ample processing power for today's emerging multimedia and digital consumer applications.
In its most basic RISC/DSP configuration, the ARC 600 represents the lowest power and smallest cores in the industry.
Whether the target is small size, low power, or high performance, the architecture enables system designers to find the proper balance for their design.
A key component of the ARC 600 development platform is the ARChitect tool,which is used to help designers find the optimum balance between speed, area, and power.
The ARC 600 introduces, for the first time, a "CPU island" architecture that dramatically reduces required integration effort and greatly facilitates multiprocessor design.
The CPU island's completely synchronous interface supports BVCI and Amba buses and isolates the core and memory from other parts of the system such as peripherals and the system bus.
By providing this clean, preverified boundary, a designer is able to achieve timing closure more quickly while minimising time required for system verification.
Thus, system designers can instantiate one or many ARC 600s and still hit their time to market.
For mathematically intensive applications, the ARC 600 offers enhanced DSP performance.
Capable of 32bit arithmetic and SIMD operations, the ARC 600 defines a rich set of optional DSP instructions to speed up multimedia applications such as digital audio and VoIP.
These DSP instructions include: dual 16bit multiply/multiply-accumulate/multiply-subtract, 24bit multiply/multiply-accumulate/multiply-subtract; Viterbi butterfly instruction, FFT butterfly extension, CRC instruction, division assist instruction; and saturating add/subtract, saturating shift.
The ARC 600 also provides an optional high-bandwidth XY memory and address generation unit supporting different modes such as linear, reverse-carry, and circular addressing.
"The ARC 600 is the result of 10 years of processor experience and significant customer input.
The result is a leading class processor for the low power multimedia and consumer markets", said Mike Gulett, President and CEO of ARC International.
"The ARC 600 architecture retains the flexibility of previous ARC processors while introducing a new market standard of performance in speed, area and power, meeting a wide range of multimedia system requirements.
Indeed, we believe this new architecture is the beginning of a new roadmap for the company in configurable RISC/DSP-based systems".
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