Configurable processor technology patented

The US Patent and Trademark Office has awarded ARC International a fundamental patent relating to configurable processor technology.

The US Patent and Trademark Office (USPTO) has awarded ARC International a fundamental patent relating to configurable processor technology.

US Patent Number 6,862,563, entitled "Method and apparatus for managing the configuration and functionality of a semiconductor design", details processes and systems used to generate a description language model of a processor core using libraries containing prototype and extension logic descriptions, as well as user inputs relating to the desired core configuration and extension features.

One practical implementation of this technology is ARC International's proprietary ARChitect processor configurator.

Used by all of ARC's processor licensees, ARChitect is a Java-based design tool that greatly simplifies the core design process, and enables SoC designers to create chips that precisely meet application requirements of high-volume markets.

Using the ARChitect configurator, SoC designers can easily lower the gate count and power consumption of processors by automatically configuring, customising, extending and testing them in a software environment that resides on the user's desktop.

"This USPTO action underscores ARC's position as the industry leader in configurable technology", said Carl Schlachte, ARC's President and CEO.

"Configurability is bringing about a revolution in SoC design".

"The patent award strengthens ARC's efforts to broadly market the benefits of configurable technology to the semiconductor industry".

"Already millions of ARC-based chips are shipping to market in high-volume applications".

"As the acknowledged pioneer of configurable SoC technology, ARC can now bring the benefits of configurability to more markets and applications".

The ARChitect configurator provides a comprehensive set of tools and resources to easily customise an ARC core and integrate peripherals and other IP using a drag-and-drop GUI.

The ARChitect configurator also provides guidelines for final silicon area and memory requirements.

Included is the ability to configure features around the core such as type and size of caches, interrupts, DSP subsystem, timers and debug components, as well as features within the core such as type and size of core registers, address widths and instruction set options.

Performance and die size tradeoffs are quickly accomplished, resulting in an optimised solution.

Invariably the ARC core will be smaller and lower power than non-ARC cores with fixed configurations.

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