Core extensions ease debug tasks

ARC International has added new configurable trace and debug extensions to its ARC 600 and 700 core families.

ARC International has added new configurable trace and debug extensions to its ARC 600 and 700 core families.

The new extensions only add 5000 gates of logic compared with more than 100,000 from alternative offerings, and are seamlessly integrated into ARC's MetaWare integrated development environment and the ARChitect processor configurator.

ARC carefully analysed user requirements for software debug in real-time systems and selected the most efficient features to produce a solution which is small enough to be realistically implemented in the final chip.

"ARC's new debug and trace extensions are another way in which we are lowering the cost of SoC design using our patented configurable technology", said Peter Hutton, Senior Vice President of Engineering for ARC International.

"The extensions are small enough to allow developers who need to increase their software debug productivity to hit tight time to market windows to put them on the final chip, without killing their equally critical area and power budgets".

ARC's new debug and trace extensions are an on-chip debug hardware module that SoC designers can add to an ARC 610D, 625D, 710D, 725D or 750D core using the ARChitect processor configurator.

They increase core logic only by 5000 gates and provide powerful software development capabilities that rival in-circuit emulators.

With the debug and trace logic embedded within the CPU core, software designers have visibility into the operation of their software execution.

During trace, the debug module stores the address of any noncontiguous instruction being executed.

Thus, a designer can examine the machine state before and after a software or hardware breakpoint.

Repeating loops are identified by the LSB (least significant bit) of the flow-change source and destination addresses.

The MetaWare debugger enables the logic and displays the instruction trace history.

It will read the saved instruction trace information via the JTAG port when the processor is halted using the system clock, which will be gated when tracing is disabled.

All inputs to the debug logic will be zeroed when not in trace mode to provide additional power savings.

ARC's new extensions run at the full speed of the cores within the 600 and 700 families.

ARC's real-time trace and debug extensions will be available in Q1 2006 and come as standard components within the ARChitect processor configurator.

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