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Product category: Design and Development Software
News Release from: Asset InterTech | Subject: DFT Analyzer
Edited by the Electronicstalk Editorial Team on 03 January 2006

Analyser picks up magazine award

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Asset InterTech's DFT Analyzer has been honoured with a "Best In Test" award from Test and Measurement World.

Asset InterTech's DFT Analyzer, billed as the industry's first design-for-test tool for boundary scan (IEEE1149.1/JTAG), has been honoured with a "Best In Test" award from Test and Measurement World This marks the third consecutive year that Asset has earned Best In Test recognition

Asset is an international leader in boundary-scan test and in-system programming (ISP).

The previous two years, the company's ScanWorks JTAG system earned Best In Test honours for being the first boundary scan system to support the testing of high-speed AC-coupled buses under the IEEE1149.6 standard and for its TopCAT technology which significantly accelerates the automatic generation of JTAG tests.

Asset's DFT Analyzer was awarded an honourable mention in the 2006 Best In Test programme.

"For ScanWorks to win a Best In Test for two years running and now for DFT Analyzer to win one - we're just very excited that all of the hard work has paid off with industry recognition", said Reg Waller, European Director for Asset InterTech.

"It is particularly heartening this year because DFT Analyzer is the first in its class as a boundary scan DFT tool".

"We expect that DFT Analyzer will drive sound boundary-scan DFT practices deeper into the design process and that will generate significant benefits for manufacturers".

Asset's ScanWorks is currently deployed by leading electronics companies such as Cisco, Lucent Technologies, Agilent, BAE, Hewlett-Packard, Ericsson, Alcatel, SBS, Intel, Raytheon, Solectron, Rockwell Collins, EMC and many others.

DFT Analyzer reduces manufacturing and test costs by validating the boundary-scan DFT features in a circuit board design before any prototypes are assembled.

This can reduce expensive design respins and schedule disruptions that often result from the discovery of inadequate test coverage when a design moves from development into manufacturing.

DFT Analyzer also determines the extent of the boundary-scan test coverage and recommends changes in the design that would increase coverage.

DFT Analyzer is made up of three tools which are employed at different stages in product development.

First, as schematics are being developed, an automated checklist queries a designer about the testability features in the design.

Next, a design validation tool is launched after computer aided design (CAD) information has been compiled.

Based on the CAD data, the design validation tool determines whether established DFT rules have been broken.

Lastly, test coverage analysis is engaged during the final stages of design before prototypes are manufactured.

This tool determines the extent of boundary-scan test coverage and reports on where physical test points may be eliminated.

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