Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: Atmel Corporation | Subject: AT91SAM9261
Edited by the Electronicstalk Editorial
Team on 18 November 2005
Smart MCU aims for point-of-sale control
The AT91SAM9261 smart ARM microcontroller (SAM) is based on the ARM926EJ-S processor and is billed as the industry's first ultra-low-power deterministic microcontroller.
Atmel Corporation has developed the industry's first ultra-low-power deterministic microcontroller, the AT91SAM9261 smart ARM microcontroller (SAM), based on the ARM926EJ-S processor Targeted at low power, high throughput wireless handheld applications, such as wireless PoS devices, the AT91SAM9261 consumes only 2.5uA in standby mode
This article was originally published on Electronicstalk on 23 May 2006 at 8.00am (UK)
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Operating at 500Hz it draws 400uA.
Maximum operating power at 180MHz with all peripherals turned on is just 65mA.
The AT91SAM9261's 200MIPS throughput and its extended instruction set with DSP extensions allow complex DSP functions, such as biometrics, voice recognition, software modems, or encryption/decryption algorithms like RSA, to be executed very quickly in burst mode, so the can system be shut down much of the time.
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In a typical PoS application with a four-hour battery life, such as a rental car-return processing module, these new MCUs can extend battery life by as much a factor of four to 16 hours.
Data throughput is significantly increased by the parallelism provided by the multilayer bus matrix.
The bus matrix connects five advanced high-speed bus (AHB) bus masters (processor instruction and databuses, peripheral DMA controller and two dedicated DMAs for the USB host and LCD controller), to the on-chip peripherals and internal or external memories.
Atmel has extended the peripheral DMA control used on its ARM7-based MCUs to include 19 peripheral DMA controller channels on the AT91SAM9261.
The peripheral DMA controller offloads data transfer operations between the peripheral and memories from the CPU, dramatically increasing datarates and freeing the ARM9 CPU for compute intensive tasks.
This unique combination of the internal multilayer AHB bus architecture and the dedicated peripheral DMA controller maximises processor throughput and optimises overall system power consumption.
For example, the peripheral DMA controller can facilitate data transfers between the on-chip SRAM and peripherals while the processor simultaneously executes code out of cache or does a cache line fill.
Alternatively, the processor can execute code out of on chip SRAM deterministically in parallel to the peripheral DMA controller streaming data from peripherals to external memory.
Atmel's AT91SAM9261 has 16Kbyte of data cache, 16Kbyte of instruction/write buffer cache, 160Kbyte of 200MHz single-cycle-access SRAM, and 32Kbyte of internal ROM.
Atmel has exploited the ARM926EJ-S's tightly coupled memory (TCM) architecture that allows traditional (noncache) SRAM to be connected directly to the ARM processor, with no latency.
Separate, transparent, easy to use instruction and data caches support WinCE and Linux operating systems, and the TCM SRAM blocks are ideally suited for deterministic real-time operating systems.
The on-chip 160Kbyte of SRAM can be partitioned in multiples of 16Kbyte blocks as instruction TCM, data TCM, or a buffer for the on-chip peripherals.
It gives the programmer maximum flexibility to optimise system performance and power consumption.
The majority of PoS or other data input devices have graphical interfaces that use small LCD screens with menus.
The AT91SAM9261's on-chip LCD controller supports black-and-white and up to 16M colours, driving active TFT and passive STN LCD displays with a resolution of up to 2048x2048.
The on-chip 160Kbyte SRAM can be configured as a frame buffer, thereby minimising the BOM costs associated with an external frame buffer and increasing the battery life.
A USB host controller provides a seamless interface to any USB device, including mouse, keyboard, bar code reader, wireless LAN, DECT or Bluetooth modem.
Its dedicated DMA controller and the multilayer AHB internal bus architecture minimise the processor intervention during data transfers.
The USB device port handles connectivity to a PC for system updates and maintenance.
The ARM9 interrupt control scheme is insufficient to meet the demands of interrupt-driven real time systems.
Atmel has enhanced this scheme with an eight-level priority, individually maskable, vectored interrupt controller that can handle up to 32 internal or external interrupt sources.
Interrupt response time is reduced to a minimum.
The AT91SAM9261 has a system controller with a full complement of supervisory functions including the advanced interrupt controller, timing sources (oscillator, PLLs), real-time periodic interval and watchdog timers, reset and shutdown controllers, backup registers and real-time timer, a power management controller, a debug unit and PIO controllers that multiplex the I/O lines.
The system controller also provides configurable clocks to the processor core and each of the individual peripherals at the appropriate rates.
It also sources four programmable output clocks and enables the core and selected peripherals to be placed in idle mode to minimise power consumption.
AT91SAM9261 peripherals include periodic interval timer, watchdog timer, real time timer, three 32bit parallel I/O controllers, SD- and Multimedia-compliant Multimedia Card interface (MMC), three synchronous serial controllers, three USARTs, one debug UART, two master/slave serial peripheral interfaces (SPI), a three-channel 16bit timer/counter, two-wire interface (TWI) and IEEE1149.1 JTAG boundary scan on all digital pins.
The AT91SAM9261-EK low-cost evaluation kit supports the AT91SAM9261 and its industry-standard ARM architecture gives it compatibility with a wide range of development tools, compilers and debuggers from industry-leading third-party suppliers.
The AT91SAM9261 is available now in a 217-ball LFBGA RoHS-compliant package and is priced at $10 in quantities of 10,000 units.
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