High throughput for embedded memory

The Atmos SoC-RAM ML family of embedded memory macrocells enables embedded memories up to 128Mbit with bus widths up to 1Kbit, throughput up to 400Gbit/s and minimal soft error susceptibility.

The newly launched Atmos SoC-RAM merged logic (ML) family of embedded memory macrocells enables embedded memories up to 128Mbit with bus widths as large as 1Kbit, throughput up to 400Gbit/s and minimal soft error susceptibility.

The new product family builds on a partnership with NEC Electronics, announced earlier this year.

It takes advantage of NEC's stacked metal-insulator-metal (MIM) capacitor cell that provides better than 400MHz random access cycle speed and very low SER well under 1000FITs per macrocell, regardless of the size.

SER has become an increasing challenge for designers of high-performance chips, as embedded SRAM grows increasingly susceptible to soft error upset.

Megabit instances of embedded SRAM at 0.13um exhibit SER of 1000FITs per megabit, requiring the use of extra circuitry for error correction code (ECC).

"The SoC-RAM ML family is targeted at a host of high-bandwidth applications such as high-capacity switch fabrics, packet processors for terabit switches and optical networking equipment", summarised Mel Roberts, Senior Director Product Line Management at Atmos.

"SoC-RAM ML is ideal in products like this where high performance, speed, low latency, wide databus and low power are required".

"Our relationship with Atmos, combined with their expertise in embedded memory design, brings customers all the benefits of NEC's 0.15um merged logic embedded DRAM", said Hideya Horikawa, Senior Design Engineering Manager at the US Technology Center of NEC in Santa Clara.

"We are confident that, with the Atmos product and team, we will help our customers develop the highest speed, most innovative networking products possible".

A 64Mbit SoC-RAM ML instance will occupy just 66mm2 and typically use 500mW, ensuring fabless semiconductor and network infrastructure vendors benefit from a highly competitive product in sync with the channel densities and constrained power dissipation required in next-generation networking equipment.

In addition, the 0.15um implementation cuts memory area by a factor of 10 compared with traditional embedded six-transistor SRAM.

Using the ATMOS SoC-RAM ML compilers, designers can rapidly configure memory with bit-level granularity, minimising overall die size where multiple instances are used, and optimising for speed, area and power in just minutes.

The SoC-RAM ML family of products is the latest addition to the company's high-density embedded memory product line.

Other products include SoC-RAM SL, silicon-proven macrocells available in 0.18 and 0.13um standard logic process.

Interested customers can begin new designs with SoC-RAM ML today, using the SoC-RAM ML 8Mbit block or multiples thereof.

The compiler front end will be available in early Q1 2002.

The full SoC-RAM ML compiler with all design views is planned for Q2 2002.

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