Backplane transceiver unlocks "hidden" bandwidth

The AN6425 6.25Gbit/s quad backplane transceiver is the first of the new AN6000 family of low-power high-speed serdes transceiver products from Accelerant Networks.

The AN6425 6.25Gbit/s quad backplane transceiver is the first of the new AN6000 family of low-power high-speed serdes transceiver products from Accelerant Networks.

The AN6425 is targeted for the upgrade of existing network, server and storage systems to 6.25Gbit/s datarates and above.

The single-chip device is the industry's most efficient backplane transceiver solution, combining all of the elements needed to unlock hidden bandwidth in the backplanes of currently deployed systems: increased speed, low power, datarate flexibility and reliability.

Today's backplane datarates of 622Mbit/s to 3.125Gbit/s have traditionally been a bottleneck, limiting the amount of bandwidth existing systems can support.

Accelerant has proven that hidden, useable bandwidth exists in these deployed backplanes through actual transceiver testing at up to tenfold faster rates on more than 60 systems.

In addition to increased performance, results of these tests have clearly demonstrated the ability of the single-chip AN6425 to deliver breakthrough reliability levels, with bit error rates (BER) of better than 10e-18 across the entire range of 1 to 10Gbit/s over existing backplanes.

This reliability rating is orders of magnitude better than the industry's typical BER specification of 10e-12.

"Networking, storage and server system manufacturers all share the same desire to offer end customers enhanced port density and bandwidth to lower overall cost per bit", said Bill Hoppin, Vice President of Marketing for Accelerant Networks.

"With fewer end customers implementing wholesale changes of installed chassis, system developers are looking for cost-effective ways to upgrade their customers' existing equipment.

We believe our focus on reliable high speed transmission over existing low cost interconnects, as opposed to depending on expensive new materials and techniques, paves the way for enhanced bandwidth where systems developers need it most: in the installed base of equipment".

"Accelerant's 10Gbit/s serdes technology works great over our broadband backplanes", said John Webley, CEO of Turin Networks.

"Increased backplane link speeds support higher bandwidth blades, which means higher port densities and lower costs for our MSPP and crossconnect (DACS) customers.

The distributed fabric architecture, used in Turin's Traverse platforms, makes it possible to add blades that use higher speed backplane links without obsoleting deployed blades or requiring upgrades to any common equipment".

Based on Accelerant's intelligent silicon technology, the device uses adaptive equalisation to unlock hidden bandwidth in existing, low cost FR4 backplanes common to network, server and storage equipment currently installed worldwide.

Adaptive equalisation compensates for the loss and intersymbol interference of older, less optimal backplane interconnects and enables signal transmission up to ten times faster than previously possible.

Using Accelerant's technology, very low bit error rates are achieved with minimal power consumption and maintained over temperature and humidity.

"Rather than developing new systems, OEMs are focusing on extending the life of existing systems", said Jag Bolaria of the Linley Group.

"Accelerant offers developers the ability to operate at very high datarates over installed backplane interconnects with high reliability and low power consumption.

Consequently, system developers can offer their customers greater bandwidth while staying within power and thermal requirements of the existing chassis.

Because these upgrades consist of changes to switch and line cards only, the system does not have to be taken off line".

Accelerant's intelligent silicon technology dynamically senses the intersymbol interference of each backplane interconnect, then uses continuous feedback to adjust equalisation for optimum performance and most efficient use of power.

Accelerant is unique in its ability to combine this with both traditional binary signalling as well as proven technology leadership in multilevel signalling (pulse amplitude modulation or PAM-4) packing 2bit per clock cycle to double the data density.

Its binary signalling modes have been carefully optimised to enhance robust interoperability with other serdes devices.

Typical binary backplane transceivers operate with up to 25% of encoding overhead.

This hampers the usable datarate to 75% of the total backplane speed and requires the transceiver to understand individual coding protocols.

Accelerant's technology eliminates the overhead (0%) independent of protocol, enabling robust 100% use of the backplane speed.

The AN6000 series also features a per-channel built-in programmable bit error rate tester (BERT), an internal scope, and built in self test (BIST) for each backplane interconnect - comparable with over $60,000 of external test equipment.

This gives system developers the high level of reliability validation required at these increased datarates, and highlights the inherent signal integrity of the technology.

Accelerant achieves its extremely low power consumption of less than 1W for a quad 6.25Gbit/s backplane transceiver through optimised adaptive equalisers and low-power circuit implementation.

Low power facilitates use in dense circuit boards enabling system developers to remain within the fixed thermal budget defined by existing chassis design.

The low power AN6000 cores, now offered by Agere Systems through a previously announced partnership with Accelerant, are ideal for integration onto high-port-count ASICs.

The AN6425 is a 17 x 17mm low-cost plastic BGA device consuming less than 1W of power.

The device is sampling now and is priced at $90 per unit in volume.

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