Product category:
Communications ICs (Wired)
News Release from: Accelerant Networks | Subject: AN6420
Edited by the Electronicstalk Editorial
Team on 03 November 2003
Top performance claims for low-power
serdes
The AN6420 is heralded as the highest-performance, lowest-power serdes device available today for backplane applications.
The AN6420 is heralded as the highest-performance, lowest-power serdes device available today for backplane applications The AN6420 is the newest member of its AN6000 family of high-speed serdes transceivers that offers breakthrough 0% overhead technology for the highest performance, lowest power serdes device available, demonstrating line rates of 10Gbit payloads (Ethernet or OC-192) across existing backplane differential pairs, without increasing the existing power budget
This article was originally published on Electronicstalk on 1 Aug 2003 at 8.00am (UK)
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This makes the AN6420 the highest performance, lowest power serdes device available today for backplane applications.
The AN6420 operates at 6.25Gbit/s with a demonstrated rate up to 10Gbit/s user payload in PAM4 multilevel signalling mode with no additional coding overhead (0% overhead), making it 25% more bandwidth efficient than typical 8B/10B coded transceivers.
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As with all Accelerant PAM4 transceivers, the AN6420 features adaptive equalisation performed by the part.
For interoperation in legacy binary modes with serdes on existing line cards, the AN6420 operates up to 5Gbit/s with a decision feedback equaliser (DFE) in the receiver enabling it to offer robust operation independent of the quality of the legacy link.
For legacy upgrades the AN6420 includes the world's first binary backplane DFE implementation, allowing error-free operation at speeds up to 5Gbit/s even with eyes that are completely closed.
This insures interoperability with the binary serdes typical of the installed base of system line cards, enabling greater opportunities for system developers to upgrade existing network, server, and system chassis backplanes to higher performance.
"Maintaining a reasonable power budget, operating over low-cost interconnects, and interoperating with existing hardware have been the primary obstacles to upgrading existing backplanes to higher speed performance", said Bill Hoppin, Vice President of Marketing for Accelerant.
"System developers have now designed Accelerant's AN6000 series into strategic upgrade projects that result in fundamental changes to product lifecycle at the system level.
In addition, the technology is available now in an ASIC flow that provides the same functionality and power advantages of the discrete AN6420".
Many system vendors depend on ASIC integration to create key differentiation.
Typically, technology available in the form of discrete merchant ICs has outpaced that available in ASIC cores by at least a generation.
In backplane serdes technology, power per user gigabit is the ultimate metric when integrated as an ASIC core.
The availability of Accelerant's leading edge, low power-per-user gigabit per second technology both as a discrete IC and in an ASIC flow simultaneously is significant, as system developers will have greater design flexibility and cost-effectiveness both for today's upgrades and for tomorrow's next generation system designs.
The AN6420 is built with Accelerant's new modular development architecture such that each building block can be re-used and optimised for custom applications and integration into ASIC designs.
Power consumption and die size of each building block are extremely low, and are optimised for either backplane interconnect or chip-to-chip applications.
The 130nm AN6420 core is available today from Agere Systems in its ASIC flow.
Accelerant's building blocks are also ideal for future cores integrated on 90nm CMOS optimised for further improvements in die density and low power.
The AN6420 is a 17 x 17mm low-cost plastic BGA device, is sampling now, and is priced at $80 per unit in volume.
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