Product category:
Design and Development Software
News Release from: Atrenta | Subject: SpyGlass 3.0
Edited by the Electronicstalk Editorial
Team on 16 January 2002
Analysis tool checks structure of RTL
code
SpyGlass 3.0 from Atrenta is a predictive analysis tool that cuts IC design time by providing the industry's first structural analysis of RTL (register transfer level) code.
SpyGlass 3.0 from Atrenta is a predictive analysis tool that cuts IC design time by providing the industry's first structural analysis of RTL (register transfer level) code With its built-in fast synthesis engine, SpyGlass 3.0 can detect very complex structural problems at RTL that otherwise only show up at the gate level
This article was originally published on Electronicstalk on 5 Apr 2002 at 8.00am (UK)
Related stories
Simulator option speeds up Verilog RTL
SpyGlass for VCS is an option for Atrenta's SpyGlass 3.0 that improves RTL descriptions, which speeds up VCS simulation performance.
Analysis tool checks testability of RTL code
Atrenta's SpyGlass DFT incorporates two new engines to find testability issues at register transfer level (RTL) that would normally only be identified at the gate level.
SpyGlass 3.0's new graphical user interface correlates the RTL coding violations with schematics (automatically generated) to help designers get to the source of the problem and figure out the best way to debug their design.
By being able to predict where RTL code will cause problems later in the design cycle, SpyGlass helps eliminate time-consuming design iterations.
The designs created are better optimised, reusable, and go through the design flow with minimal problems.
Further reading
Trade-in deal to woo Avant! users
Atrenta has launched an aggressive trade-in programme that allows designers with Nova-ExploreRTL, Nova-VeriLint and Nova-VHDLint (VeriLint) licenses to upgrade to Atrenta's SpyGlass software.
Tool brings order to mixed-IP SoC designs
SpyGlass SoC is the first design tool to address the logical issues designers encounter when integrating multiple IP blocks from different vendors and design teams into one complex SoC design.
Predictive analysis demos at DAC
Atrenta is offering IC designers an opportunity to see first hand why leading electronic and semiconductor companies are using its predictive analysis products before running simulation or synthesis.
An independent survey by Seidman Consulting found that by using SpyGlass, designers can achieve a 15-20% reduction in the time to get new chips to market and a 10-15% reduction in design costs.
This survey also found a sixfold reduction in ramp-up time for knowledge capture and a 60% reduction in compliance checking for design reuse.
SpyGlass 3.0 uses predictive analysis to look at the structure of the design, finding downstream problems that are not detectable by other methods including other rule checkers, simulators and formal verifiers.
Atrenta has developed a novel technology that uses fast synthesis to create a gate-level representation so true structural analysis can be performed during the RTL design phase.
New checks include tests that can predict problems with complex clock synchronisation, tristate bus decoders, combinational loops, logic cone depth, and read-before-write in sequential circuits.
SpyGlass employs a proprietary fast synthesis engine that can synthesise a large, 3-million-gate design in less than 30min.
Synthesis allows SpyGlass to look at the hierarchy in the design, checking for issues with inferred objects, such as inferred latches, flip flops, muxes and counters.
Then SpyGlass takes the hierarchical gate-level structure and flattens it, looking for complex problems such as combinational loops, decoding errors, multiclock domains and complex synchronisation problems that often aren't even found in simulation.
One of the biggest benefits of SpyGlass' ability to delve deep into the structure of the design is that it can do in-depth tests.
"If the design is very complex with parameters, complex loops and multiple levels of hierarchy, simple rule checkers are easily fooled into generating false error reports", stated Dr Bernard Murphy, Atrenta's Vice President of Product Development.
"SpyGlass's built-in synthesis engine allows us to accurately expose the underlying design structure and thus eliminate the primary causes of false errors".
SpyGlass 3.0's new GUI can display a schematic of the synthesised logic so designers can cross-probe between their RTL code and the schematic.
As the software is completely contained within the SpyGlass package, accurate pointers are maintained from both the synthesis level and the flat level back to the source RTL.
Violations are highlighted on the schematic along with the corresponding RTL code.
Designers can cross-probe between RTL and schematic views to get a good understanding of the problem and how it might best be fixed.
Because conventional synthesis does not, by default, share resources, often silicon real estate is wasted.
If overlooked, increased die sise and power requirements are noticed when it is much too late to change the design.
By evaluating the RTL code at a structural level, SpyGlass can find places where resources can be shared thereby optimising area and power consumption.
Additionally, because SpyGlass includes a fast synthesis engine, it can provide designers with an early rough gate count for their design.
This lets designers do trade-off analysis early in the design cycle and experiment with the gate-count-costs involved in different design techniques.
SpyGlass can give gate-count and logic depth information down to the module level, so designers can pinpoint areas that are consuming the most real estate and, potentially, cause timing problems and higher power consumption.
SpyGlass 3.0 provides new customisation analysis so the designer can add rules, enable and disable tests, and establish profiles that store a designer's selection of policies, rules and parameters.
Designers can choose among various policy decks and rule sets that are organised by functional requirements, such as area, timing, and clocks, and by application selection, such as best practices, RTL handover, synchronous design, and by rules for specific vendors' tools.
Designers can use either the PERL or C programming languages for this customisation.
SpyGlass 3.0 is available now.
Pricing starts at $60,000 per year for an entry package.
SpyGlass runs on Sun/Solaris 2.5 - 2.8, HP-UX 10.2 and RedHat Linux 6.2 and above.
SpyGlass supports VHDL and Verilog, and includes a new rule set for Verilog 2000.
It is compatible with industry-wide design tools and environments, assuring that it can be used seamlessly within a customer's current design flow.
(This was Electronicstalk's Top Story on 15 January 2002).
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