Product category:
Design and Development Software
News Release from: Atrenta | Subject: SpyGlass DFT
Edited by the Electronicstalk Editorial
Team on 17 January 2002
Analysis tool checks testability of RTL
code
Atrenta's SpyGlass DFT incorporates two new engines to find testability issues at register transfer level (RTL) that would normally only be identified at the gate level.
SpyGlass DFT is the latest addition to Atrenta's popular SpyGlass predictive analysis tool that adds two new engines to find testability issues at RTL (register-transfer level) that normally only can be identified at the gate level According to Atrenta, no other tool can provide the comprehensive range of testability analysis offered by SpyGlass DFT
This article was originally published on Electronicstalk on 16 Jan 2002 at 8.00am (UK)
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Analysis tool checks structure of RTL code
SpyGlass 3.0 from Atrenta is a predictive analysis tool that cuts IC design time by providing the industry's first structural analysis of RTL (register transfer level) code.
Simulator option speeds up Verilog RTL
SpyGlass for VCS is an option for Atrenta's SpyGlass 3.0 that improves RTL descriptions, which speeds up VCS simulation performance.
SpyGlass DFT includes rules for ATPG and BIST.
If RTL designers don't properly apply testability rules at the initial design stage, the design can have poor test coverage or even be untestable until extensive changes are made.
By letting designers write their RTL code to comply with testability rules before lengthy synthesis and simulation cycles, SpyGlass DFT can cut weeks or months off design cycles, eliminating or reducing gate-level debug and costly schedule delays.
Further reading
Trade-in deal to woo Avant! users
Atrenta has launched an aggressive trade-in programme that allows designers with Nova-ExploreRTL, Nova-VeriLint and Nova-VHDLint (VeriLint) licenses to upgrade to Atrenta's SpyGlass software.
Tool brings order to mixed-IP SoC designs
SpyGlass SoC is the first design tool to address the logical issues designers encounter when integrating multiple IP blocks from different vendors and design teams into one complex SoC design.
Predictive analysis demos at DAC
Atrenta is offering IC designers an opportunity to see first hand why leading electronic and semiconductor companies are using its predictive analysis products before running simulation or synthesis.
Also, SpyGlass DFT can help ensure that RTL code is reusable in future designs.
"RTL designers typically don't have visibility into testability issues, but are expected to comply with DFT rules", stated Dr Ajoy Bose, chairman, president and CEO of Atrenta.
"Test engineers are often forced to make gate-level changes, which breaks the link to RTL.
SpyGlass DFT solves this problem by identifying testability issues in the RTL up front, and ensures testable netlists for downstream tools".
"By catching errors during design capture, weeks and even months can be shaved off project schedules", said Bose.
"When changes are not found until the gate level, engineers have to go back and repeat their lengthy simulations that's the real time killer that often leads to cost overruns and loss of market window opportunities".
SpyGlass DFT helps minimise development cost overruns, achieve more predictable schedules, improve design quality and performance, lower project cost and increase design reuse.
Other DFT tools operate at the gate level, after synthesis and simulation.
However, changes made at this point are not reflected in the RTL.
Therefore, the same problems must be found each time the RTL is reused.
Also, the cost of adding testability compliance late in the design cycle can be tremendous.
SpyGlass DFT analysis extends far beyond simple topology checks.
It includes 66 advanced checks for clocks, latches, tristate busses, RAM, scan insertion, and more.
For example, SpyGlass DFT can find complex issues such as sequential feedback loops that can't be initialised, tristate busses with contention possibility, scan chains with mixed edges, and problematic feedback loops.
SpyGlass DFT can analyse a design before any DFT logic is added to pinpoint where basic controls must be added.
As design for testability changes are made, SpyGlass DFT will verify that these changes function as required as well as highlight where additional changes are still required.
Designers can also add custom rules that help SpyGlass check for deep structural problems or special DFT considerations.
Designers can use either the PERL or C programming languages for this customisation.
Atrenta has also developed SpyGlass-LogicVision, a customised DFT solution for LogicVision users.
With SpyGlass-LogicVision, designers can ensure that LogicVision's embedded test insertion requirements are taken into account early in the semiconductor's design cycle.
Many issues are not easily apparent in RTL code because testability depends on implementation and functionality.
Because SpyGlass DFT is built on powerful engines that can thoroughly examine the structure of the design, it can find much more complex issues than conventional rule checkers.
With conventional rule-checkers, false errors tend to overwhelm designers, who face the challenge of going through hundreds of error reports to find the "real" errors.
SpyGlass DFT adds two engines to the SpyGlass predictive analysis tool.
Designers using SpyGlass DFT actually have five powerful engines to provide advanced analysis of RTL code.
The three SpyGlass engines include RTL checking (often referred to as linting, the line-by-line semantic check of the code), local structure (a fast synthesis engine that checks the design's hierarchy) and global structure (the flattening of the design to find complex structural problems).
SpyGlass DFT adds an engine for functional analysis and another engine for testability analysis.
The functional analysis engine is a cycle-based simulator that can simulate test mode conditions.
This lets SpyGlass do localised simulations to test aspects of the functionality of the design, not just the connectivity of the design.
This is particularly useful in DFT where SpyGlass can, for example, set a test mode and then verify that internally generated clocks have been properly bypassed for scan operations.
Without simulation, these complex issues could not be identified.
The testability analysis engine checks for controllability and observability as well as initialisation issues for BIST compliance.
For the first time, testability analysis is available at the register-transfer-level so that designers can quickly evaluate the testability impact of design changes.
This powerful engine also provides an efficient means to identify the amount of shadowed logic on a RAM-by-RAM basis as well as the amount of logic blocked when adding test mode controls.
Both of these new engines produce results that are fully back-referenced to the original RTL source code so that error messages and reports point directly to the source language (Verilog or VHDL).
Designers can cross-probe between RTL and schematic views to quickly understand the issues and how they might best be fixed.
SpyGlass DFT is ideal for large designs with 2 million gates or more because these expensive designs must be done right the first time or cost overruns can be significant.
However, even in designs as small as 250,000 gates, testability issues can be expensive, especially if the schedule is very tight.
SpyGlass DFT focuses the designer on the precise cause of the test problem so that changes can be made quickly.
And, because of its multi-million-gate capacity, entire designs can be checked thereby ensuring total compliance with DFT rules.
SpyGlass DFT is available now for $25,000/year option to SpyGlass.
SpyGlass DFT runs on Sun/Solaris 2.5 2.8, HP-UX 10.2 and RedHat Linux 6.2 and above.
It is compatible with industry-wide design tools and environments, assuring that it can be used seamlessly within a customer's current design flow.
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