Product category:
Design and Development Software
News Release from: Atrenta | Subject: SpyGlass trade-in deal
Edited by the Electronicstalk Editorial
Team on 16 April 2002
Trade-in deal to woo Avant! users
Atrenta has launched an aggressive trade-in programme that allows designers with Nova-ExploreRTL, Nova-VeriLint and Nova-VHDLint (VeriLint) licenses to upgrade to Atrenta's SpyGlass software.
Atrenta has launched an aggressive trade-in programme that allows designers with Nova-ExploreRTL, Nova-VeriLint and Nova-VHDLint (VeriLint) licenses to upgrade to Atrenta's SpyGlass software Under this limited-time offer that expires on 30th June 2002, one SpyGlass license is free for every two VeriLint licenses that are traded in for two SpyGlass licenses
This article was originally published on Electronicstalk on 16 Jan 2002 at 8.00am (UK)
Related stories
Analysis tool checks structure of RTL code
SpyGlass 3.0 from Atrenta is a predictive analysis tool that cuts IC design time by providing the industry's first structural analysis of RTL (register transfer level) code.
Analysis tool checks testability of RTL code
Atrenta's SpyGlass DFT incorporates two new engines to find testability issues at register transfer level (RTL) that would normally only be identified at the gate level.
"With the pending acquisition of Avant!, future support for Nova-ExploreRTL and the Verilint product family is a serious question and a big concern for the users of these products", stated Ghulam Nurie, senior vice president of marketing and business development at Atrenta.
"In addition to ensuring future support and enhancements, Atrenta's trade-in program offers a great opportunity for Avant! customers to move up to SpyGlass, a predictive analysis product with many advanced capabilities not found in Avant!'s products.
In addition to basic linting capability, SpyGlass offers checks for very complex design problems such as clock domain crossings, timing issues, area estimation and one-hot checks".
Further reading
Simulator option speeds up Verilog RTL
SpyGlass for VCS is an option for Atrenta's SpyGlass 3.0 that improves RTL descriptions, which speeds up VCS simulation performance.
Tool brings order to mixed-IP SoC designs
SpyGlass SoC is the first design tool to address the logical issues designers encounter when integrating multiple IP blocks from different vendors and design teams into one complex SoC design.
Predictive analysis demos at DAC
Atrenta is offering IC designers an opportunity to see first hand why leading electronic and semiconductor companies are using its predictive analysis products before running simulation or synthesis.
Atrenta's SpyGlass employs a novel predictive analysis technique that looks at the structure of the RTL design and finds down-stream problems that are not detectable by other methods including other rule checkers, simulators and formal verifiers.
Atrenta has developed a unique technology that uses fast synthesis to create a gate-level representation so true structural analysis can be performed during the RTL design phase.
In addition, this innovative "look-ahead" capability incorporates a simulator and a testability engine to perform dynamic analysis and true testability analysis while the design is still at RT level.
This enables SpyGlass to detect at the RT level very complex design problems such as clock synchronisation, tristate bus decoders, combinational loops, DFT issues, logic cone depth, and race conditions in sequential circuits.
A new graphical user interface with a schematic browser for the synthesised view pinpoints design violations on the original RTL for quick problem isolation and debugging.
SpyGlass provides a powerful environment where reuse requirements and best practices can be captured, consolidated and used to analyse a design.
A broad collection of configurable policies is available with SpyGlass in both VHDL and Verilog.
These policies include over 2500 rules and guidelines covering coding style, design practices, DFT, OpenMORE and other advanced checks.
In addition, special policies are available to optimise performance for Synopsys' VCS simulator and to provide compliance with LogicVision Memory BIST and Logic BIST requirements.
Custom policies are easily developed in either PERL or C.
Direct access to internal SpyGlass data structures is provided through the same SpyGlass API that is used by Atrenta's internal developers and partners.
This enables access both to RT-level and post-synthesis gate structures to facilitate the development of highly sophisticated rules that can be used in a high performance interactive environment.
SpyGlass also provides sample policies that provide users a way to jump-start their customisation efforts.
• Atrenta: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
