Product category:
Design and Development Software
News Release from: Atrenta | Subject: SpyGlass SoC
Edited by the Electronicstalk Editorial
Team on 22 May 2002
Tool brings order to mixed-IP SoC
designs
SpyGlass SoC is the first design tool to address the logical issues designers encounter when integrating multiple IP blocks from different vendors and design teams into one complex SoC design.
SpyGlass SoC is the first design tool to address the logical issues designers encounter when integrating multiple IP blocks from different vendors and design teams into one complex SoC design By using SpyGlass SoC to create a logical virtual prototype, designers can predict and eliminate problems that normally only show up much later in the design process
This article was originally published on Electronicstalk on 16 Jan 2002 at 8.00am (UK)
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Analysis tool checks structure of RTL code
SpyGlass 3.0 from Atrenta is a predictive analysis tool that cuts IC design time by providing the industry's first structural analysis of RTL (register transfer level) code.
Analysis tool checks testability of RTL code
Atrenta's SpyGlass DFT incorporates two new engines to find testability issues at register transfer level (RTL) that would normally only be identified at the gate level.
With SpyGlass SoC, design teams can cut their overall SoC design times by 20 to 30%, according to company estimates.
"Integrating multiple blocks into a single SoC design has become a huge productivity issue", stated Darren Wedgwood, EDA Development and Synthesis Methodology Manager, Motorola Semiconductor.
"With SpyGlass SoC, we can identify synthesis, DFT and Motorola Semiconductor Re-Use Standards compliance issues up front, when each block is created.
Further reading
Simulator option speeds up Verilog RTL
SpyGlass for VCS is an option for Atrenta's SpyGlass 3.0 that improves RTL descriptions, which speeds up VCS simulation performance.
Trade-in deal to woo Avant! users
Atrenta has launched an aggressive trade-in programme that allows designers with Nova-ExploreRTL, Nova-VeriLint and Nova-VHDLint (VeriLint) licenses to upgrade to Atrenta's SpyGlass software.
Predictive analysis demos at DAC
Atrenta is offering IC designers an opportunity to see first hand why leading electronic and semiconductor companies are using its predictive analysis products before running simulation or synthesis.
SpyGlass saves us significant time and expensive EDA tool license usage on our SoC projects by eliminating the need for extensive iterations to solve these issues later in the design cycle".
To manage the complexity, SoC designs are divided among multiple design teams and important blocks of the design are often re-used or purchased from third parties.
Integrating all of these blocks has become a major issue.
What if different blocks have different clocking schemes? What if parts of the design don't include test mode bypass for ATPG? What if most of the blocks use a positive edge reset, but some reset on the negative edge? What if parts of the design violate best practice rules for down-stream design tools? These issues and much more, arise from the logical design, not the physical design.
A lot of attention has been paid to solving the physical aspects of SoC integration and there are many tools available for creating a silicon virtual prototype.
However, the silicon virtual prototype isn't concerned with the logical architecture of the chip.
So, with a physical virtual prototype, a chip with any number of logical errors can make it through the physical design process.
"Creating a logical virtual prototype is even more important than creating a silicon virtual prototype", stated Atrenta's President and CEO, Dr Ajoy Bose.
"A design may place-and-route beautifully but contain logical errors that render it useless.
Even one such error may cause extensive design iterations and silicon respin.
With SpyGlass SoC, the designers and system integrators can get it right the first time and eliminate the most vexing integration problems".
Jonathan Yee, President and CEO, JTA Research, Incorporated added, "SpyGlass SoC works like a polariser.
It takes our design and integration requirements and aligns all the RTL blocks for quick integration.
It creates a level of consistency and reusability in our IP sourcing chain as well as the design practices and ensures that the all the blocks and the IP fit the SoC integration standards that the design flow requires".
SpyGlass SoC employs a novel predictive analysis technique that includes the structure and function of the design and finds problems in RTL that are not easily detectable by other methods including rule checkers, simulators and formal verifiers.
SpyGlass SoC addresses key SoC integration issues including clock phasing, synchronisation, verification, reuse, and testability.
The presence of multiple clock domains in a SoC design is a common source of some of the most time-consuming design issues.
Signals generated in one clock domain may be consumed in other clock domains.
Correct operation of a chip can only be ensured if rules governing correct use of signals across asynchronous clock boundaries are followed.
SpyGlass SoC identifies signal paths that cross clock domains and analyses whether paths conform to selected synchronisation rules.
Critical verification and testability issues are quickly identified by SpyGlass SoC.
SpyGlass SoC detects problematic race conditions and combinational loops at the full-chip level prior to synthesis and simulation.
SpyGlass ensures that test mode controls, built into lower level blocks, are compatible and that test clock domains are synchronised.
This is extremely important because these problems usually cannot be discovered until the RTL is synthesised and flattened to remove the hierarchy.
Even then, these errors often are not caught until test verification, months into the design process, requiring weeks of rework just to get back to a clean gate-level design, let alone fixing the original RTL.
SpyGlass is designed to pin point complex design issues directly back into the RTL code and provide intuitive graphical and textual based output to accelerate problem diagnosis.
Rules that depend on unblocked paths not only identify the paths in question but also highlight the gate or element where blocking occurs, thereby focusing the designer's attention not only on the existence of a problem but also on the most likely cause.
SpyGlass SoC is bundled with the base SpyGlass product at no additional charge.
SpyGlass runs on Sun/Solaris 2.5 - 2.8, HP-UX 10.2, HP-UX 11 and RedHat Linux 6.2 and above.
SpyGlass supports VHDL and Verilog.
It is compatible with industry-wide design tools and environments, assuring that it can be used seamlessly within a customer's current design flow.
(This was Electronicstalk's Top Story on 21 May 2002).
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