Product category:
Design and Development Software
News Release from: Atrenta | Subject: Demos at DAC
Edited by the Electronicstalk Editorial
Team on 06 June 2002
Predictive analysis demos at DAC
Atrenta is offering IC designers an opportunity to see first hand why leading electronic and semiconductor companies are using its predictive analysis products before running simulation or synthesis.
Atrenta is offering integrated circuit designers a unique opportunity to see first hand why leading electronic and semiconductor companies are using its predictive analysis products before running simulation or synthesis At this year's Design Automation Conference (DAC), 10th-12th June 2002 in New Orleans, Atrenta will demonstrate its SpyGlass family of predictive analysis products
This article was originally published on Electronicstalk on 16 Jan 2002 at 8.00am (UK)
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Analysis tool checks structure of RTL code
SpyGlass 3.0 from Atrenta is a predictive analysis tool that cuts IC design time by providing the industry's first structural analysis of RTL (register transfer level) code.
Analysis tool checks testability of RTL code
Atrenta's SpyGlass DFT incorporates two new engines to find testability issues at register transfer level (RTL) that would normally only be identified at the gate level.
These products help predict and identify SoC integration issues, testability issues and RTL (register-transfer level) handover issues that normally only show up much later in the design process.
By fixing these problems early, designers can significantly cut their SoC design time.
Engineers can see Atrenta's SpyGlass products in booth 2925 or sign up for an in-depth demonstration in suite 4006.
Atrenta will be highlighting three new products introduced earlier this year: SpyGlass SoC, SpyGlass DFT and SpyGlass 3.0.
SpyGlass SoC enables design teams to carefully evaluate incoming IP (intellectual property) and internally designed RTL blocks to ensure it meets project guidelines.
In addition to hookup checks, SpyGlass SoC zeroes in on tough issues that often cause significant delays in SoC integration, such as race conditions, clock synchronisation, set/reset consistency and much more.
This aligns all the blocks for quick integration and eliminates schedule delays caused by inconsistent design practices.
SpyGlass DFT focuses testability analysis at the RTL development stage, detecting problems and guiding designers to the best possible solutions.
This proactive approach lets designers know, right from the start, if their design is scan ready and if the required fault coverage will be met.
SpyGlass DFT pinpoints un-testable logic and suggests changes that let designs speed through the testing process.
SpyGlass 3.0 identifies complex design problems and downstream tool flow issues right up front at RTL creation time, resulting in early detection of problems, fewer design iterations and early time to market.
RTL problems that cause handover issues, including timing and layout problems, are detected early in the design cycle.
SpyGlass reports on logic depth between registers by source and destination clock domains, snake paths that may create floorplanning and timing issues, un-driven signals, and dead-code.
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