Product category:
Design and Development Software
News Release from: Atrenta | Subject: SpyGlass
Edited by the Electronicstalk Editorial
Team on 12 July 2002
Predictive analysis aids Virtex designs
Atrenta has added new capabilities and Virtex-specific rules to its SpyGlass software.
Atrenta has added new capabilities and Virtex-specific rules to its SpyGlass software Atrenta worked directly with Xilinx to define, develop and test a comprehensive set of rules that helps designers identify downstream issues early in the design cycle
This article was originally published on Electronicstalk on 16 Jan 2002 at 8.00am (UK)
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Analysis tool checks structure of RTL code
SpyGlass 3.0 from Atrenta is a predictive analysis tool that cuts IC design time by providing the industry's first structural analysis of RTL (register transfer level) code.
Analysis tool checks testability of RTL code
Atrenta's SpyGlass DFT incorporates two new engines to find testability issues at register transfer level (RTL) that would normally only be identified at the gate level.
This specialised rule deck for SpyGlass performs structural analysis on Verilog and VHDL RTL code to help ensure that code meets advanced design requirements and FPGA design best practices.
Unlike conventional RTL checkers that simply analyse the text and infer potential problems, SpyGlass employs predictive analysis technologies including fast-synthesis and logic evaluation to create a structural representation of the RTL in order to perform in-depth analysis early in the design cycle.
This allows SpyGlass to be more precise in pinpointing problems while more accurately guiding the user to the best results.
Further reading
Simulator option speeds up Verilog RTL
SpyGlass for VCS is an option for Atrenta's SpyGlass 3.0 that improves RTL descriptions, which speeds up VCS simulation performance.
Trade-in deal to woo Avant! users
Atrenta has launched an aggressive trade-in programme that allows designers with Nova-ExploreRTL, Nova-VeriLint and Nova-VHDLint (VeriLint) licenses to upgrade to Atrenta's SpyGlass software.
Atrenta developed an extensive set of rules focused on helping the user quickly identify RTL constructs that should be changed to ensure compliance and best practices.
SpyGlass also detects potential synthesisability and simulation problems in the RTL, thus avoiding time-consuming rework.
"Xilinx is pleased to partner with Atrenta in order to bring advanced analysis capabilities to help customers optimise their RTL when targeting the Virtex family of Xilinx FPGAs", said Rich Sevcik, senior vice president, FPGA Products at Xilinx.
"SpyGlass' unique and innovative predictive analysis will help streamline the Platform for Programmable Systems design process that Xilinx FPGAs now offer in our VirtexII and VirtexII-pro series".
The first release of this exclusive Xilinx predictive analysis solution is comprised of an extensive set of rules that includes Virtex-specific rules and good FPGA design practices.
SpyGlass also checks for advanced design issues like: ensuring that all inferred registers use synchronous resets; ensuring that FSMs (finite state machines) are coded into separate processes; detecting combinational feedback loops; and checking that multiple clocks are not part of the same always block or process statement, and many more.
"We are happy to work with Xilinx to bring products to market that increase productivity for our common customers", said Dr Bernard Murphy, vice president and chief technical officer at Atrenta.
"We believe SpyGlass will provide Xilinx users with an automated approach to enforce advanced design rules and play a crucial role in meeting engineering schedules".
This Xilinx-specific rule set is included in SpyGlass 3.1 at no extra charge, and is sold and supported by Atrenta and its distributors.
It runs on Sun/Solaris 2.5-2.8, HP-UX 10.2 and RedHat Linux 7.
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