Product category:
Design and Development Software
News Release from: Atrenta | Subject: SpyGlass Predictive Analyzer
Edited by the Electronicstalk Editorial
Team on 07 November 2002
Rule set enforces IP re-use guidelines
SpyGlass Predictive Analyzer now includes the new STARC policy, an extensive set of analyses based on the widely used HDL Design Style Guide by HD Lab.
The Atrenta SpyGlass Predictive Analyzer now includes the new STARC (Semiconductor Technology Academic Research Centre) policy, an extensive set of analyses based on the widely used HDL Design Style Guide by HD Lab The HDL Design Style Guide is a book of standards for design guidance and design rules, developed jointly by HD Lab and STARC, a consortium of 11 major Japanese semiconductor companies that promotes a design standard for IP trade and reuse
This article was originally published on Electronicstalk on 16 Jan 2002 at 8.00am (UK)
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Analysis tool checks structure of RTL code
SpyGlass 3.0 from Atrenta is a predictive analysis tool that cuts IC design time by providing the industry's first structural analysis of RTL (register transfer level) code.
Analysis tool checks testability of RTL code
Atrenta's SpyGlass DFT incorporates two new engines to find testability issues at register transfer level (RTL) that would normally only be identified at the gate level.
Atrenta partnered with HD Lab to automate these guidelines as SpyGlass rules that enable ASIC and SoC designers to perform in-depth structural analysis on Verilog and VHDL register transfer level (RTL) descriptions and ensure compliance with best practices and IP reuse guidelines based on the STARC rules.
"The STARC policy represents the collective knowledge of eleven major Japanese corporations that worked together to produce best practices guidelines for designing reusable IPs and complex SoCs in a very efficient manner", stated Dr Toyoki Takemoto, President and CEO of STARC.
"Several years of research proven by practical results were involved in developing these design guidelines - it is one of the most comprehensive collections of best design practices".
Further reading
Simulator option speeds up Verilog RTL
SpyGlass for VCS is an option for Atrenta's SpyGlass 3.0 that improves RTL descriptions, which speeds up VCS simulation performance.
Trade-in deal to woo Avant! users
Atrenta has launched an aggressive trade-in programme that allows designers with Nova-ExploreRTL, Nova-VeriLint and Nova-VHDLint (VeriLint) licenses to upgrade to Atrenta's SpyGlass software.
Tool brings order to mixed-IP SoC designs
SpyGlass SoC is the first design tool to address the logical issues designers encounter when integrating multiple IP blocks from different vendors and design teams into one complex SoC design.
"The HDL Design Style Guide is packed with STARC's proven techniques, know-how and design rules, which lead to successful SoC projects, design re-use initiatives and IP development", said Yoshifumi Nagano, President of HD Lab.
"Atrenta has developed a comprehensive set of analyses based on the Guide to help users quickly identify RTL style that should be followed to ensure compliance and best practices".
"To successfully complete large design projects, design re-use and use of IP provided by 3rd parties is a must", said Tadahiko Nakamura, Vice President and General Manager, IP Development Department, STARC.
"The STARC guideline is an important milestone in standardizing on the best design practice for IP reuse.
Atrenta's STARC policy for SpyGlass is one of the most versatile and easy to use analysis tool for RTL design engineers who want to benefit from the STARC guidelines".
"The STARC guidelines are the 'best of the best' IP reuse guidelines assembled in one place", said Dr Ajoy Bose, Chairman, President and CEO of Atrenta.
"Atrenta's SpyGlass leverages this knowledge and expertise and brings the benefits of Japan's best practices to the design community worldwide.
The STARC policy is a major step in Atrenta's progress towards bringing the best design techniques in the industry to its customers".
The STARC Policy for SpyGlass performs in-depth structural analysis on Verilog and VHDL RTL to ensure IP reuse guidelines are followed for ASIC and SoC designs, reducing iterations and rework and speeding new designs through IP portability.
To ensure compliance and best practices according to the STARC guidelines, SpyGlass leverages STARC design expertise to quickly identify RTL constructs that should be changed.
It includes a comprehensive set of analyses focused on such areas as synchronous design, initial reset conditions, hierarchical design, asynchronous circuits, clocks, and much more.
SpyGlass offers the STARC guidelines as rules for both Verilog and VHDL analysis.
STARC is now available as part of SpyGlass Predictive Analyzer at no additional charge.
It supports both Verilog and VHDL.
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