Product category:
Design and Development Software
News Release from: Atrenta | Subject: SpyGlass
Edited by the Electronicstalk Editorial
Team on 25 November 2002
Predictive analyser for comprehensive
ASIC handoff
Agere has selected Atrenta's SpyGlass, the industry's only predictive analyser, as its ASIC handoff tool.
Agere has selected Atrenta's SpyGlass, the industry's only predictive analyser, as its ASIC handoff tool SpyGlass analyses gate-level netlists for design rule violations, allowing Agere's ASIC customers to identify potential design issues before handoff to Agere for final design and manufacturing
This article was originally published on Electronicstalk on 16 Jan 2002 at 8.00am (UK)
Related stories
Analysis tool checks structure of RTL code
SpyGlass 3.0 from Atrenta is a predictive analysis tool that cuts IC design time by providing the industry's first structural analysis of RTL (register transfer level) code.
Analysis tool checks testability of RTL code
Atrenta's SpyGlass DFT incorporates two new engines to find testability issues at register transfer level (RTL) that would normally only be identified at the gate level.
SpyGlass has a robust set of capabilities that allows ASIC providers like Agere to deliver advanced design rules and analyses to their customers who require innovative design technologies for their complex product development.
Agere will provide SpyGlass software to its customers through a flexible web-based delivery method.
"Agere is providing Atrenta's SpyGlass as part of the comprehensive suite of industry-leading design tools our customers require to help enable faster time to market at lower cost", said Cindy Genther, Marketing Director for Agere's ASIC business.
Further reading
Simulator option speeds up Verilog RTL
SpyGlass for VCS is an option for Atrenta's SpyGlass 3.0 that improves RTL descriptions, which speeds up VCS simulation performance.
Trade-in deal to woo Avant! users
Atrenta has launched an aggressive trade-in programme that allows designers with Nova-ExploreRTL, Nova-VeriLint and Nova-VHDLint (VeriLint) licenses to upgrade to Atrenta's SpyGlass software.
Tool brings order to mixed-IP SoC designs
SpyGlass SoC is the first design tool to address the logical issues designers encounter when integrating multiple IP blocks from different vendors and design teams into one complex SoC design.
"More than any other ASIC provider, we are focused on providing the highest level of service-centred operations to our customers, and this tool is another one of those differentiating ASIC services Agere provides".
Agere chose SpyGlass because it offered a comprehensive solution upon which advanced design audits can be developed.
By enhancing SpyGlass with Agere's internally developed design audit and handoff tools, Agere can offer a more robust process to help ensure first-pass success.
"SpyGlass provides a new level of analysis for our customers making it faster and easier to achieve handoff", Genther said.
"Agere's strategy is to use the very best commercially available tools as a platform on which leading edge methodologies and solutions are built.
Use of SpyGlass by our customers reduces our risk and nonrecurring engineering charges in implementing the ASIC because it ensures Agere-process compliance".
SpyGlass supports industry standard file formats like Verilog, VHDL, and Synopsys Liberty, all of which meet Agere's requirements and those of their customers.
For custom rule development, SpyGlass interfaces with C and PERL development languages to allow Agere to develop their library-specific rule deck.
The C interface provides development of complex memory and compute intensive audits, while ensuring a fast runtime.
SpyGlass provides in-depth analysis of Verilog and VHDL register transfer level (RTL) early in the design process.
Agere has extended the capability of Spyglass by providing Agere specific rules for analysing gate-level netlists for design rule violations in such areas as overloaded drivers, undesired clock interactions, electro migration violations, and intellectual property (IP)-specific errors.
"Atrenta is pleased to offer the industry's only predictive analysis platform to Agere's ASIC customers through our flexible business models and OEM sponsorships", said Dr Ajoy Bose, Atrenta Chairman, President and Chief Executive Officer.
"By catching complex design problems and process flow issues early, Agere's ASIC customers benefit from smooth, iteration free handoff to Agere for implementation.
This is truly a three-way win for Agere, Agere's customers and Atrenta".
Agere's expert knowledge in ASIC design methodology is captured in SpyGlass for their customers to leverage during the design process.
The Agere-specific rules allow SpyGlass to detect potentially fatal design issues that might be difficult, if not impossible, to identify with other methods.
While some of these problems may be detected during gate-level simulation, that approach is prohibitively slow and does not guarantee detection.
It is a real benefit to Agere's customers that they can run the Agere developed SpyGlass rules during the design process and ensure that hand-off to Agere meets all design requirements, while avoiding time consuming and costly design iterations.
Additionally, SpyGlass with the Agere rules perform both electrical and topology analysis, identifying areas of poor implementation, which although correct in function, may lead to lower circuit performance.
"SpyGlass allows Agere to standardise on a single tool for both RTL and gate level analysis", Genther said.
"In looking at alternatives, there was no other available solution that satisfied all of Agere's requirements.
We needed a robust platform to develop a comprehensive rule set that we deliver to our customers as part of our ASIC kit, and SpyGlass provides that capability".
The Agere-specific rule set is currently shipping and included in Agere's ADS301 release that is supported on Sun/Solaris 2.8 and HP-UX 11.
SpyGlass is supported on Sun/Solaris 2.5- 2.8, HP-UX 10.2 and 11.0 and RedHat Linux 7.
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