Five new patents cover IC design analysis

Edited by the Electronicstalk editorial team Feb 23, 2007

Atrenta, has been awarded five new patents by the US Patent Office for significant chip design analysis technologies.

Strengthening its leadership position in early design analysis tools, Atrenta, has been awarded five new patents by the US Patent Office for significant chip design analysis technologies.

These technologies drive Atrenta's SpyGlass tool-suite, an industry standard for design analysis.

"These technologies augment Atrenta's solution, allowing our customers to perform accurate design analysis early in the design cycle".

"As a result, they are able to make their designs correct right from RTL phase, limit design costs, as well as, save design development time", said Bernard Murphy, Atrenta's Chief Technology Officer.

US patent 6,876,934: "Method for determining fault coverage from RTL description", allows users to accurately predict the ultimate test coverage by analysing the RTL.

US patent 6,993,733: "An apparatus and method for handling of multi-level circuit design data" enables the implementation of look-ahead design methodology by evaluating the high level RTL representation of a device.

It quickly emulates the downstream implementation of the device, thus exposing potential implementation issues early in the design or manufacturing cycle.

US patent 7,076,748: "Method for efficient identification and implementation of clock gating of integrated circuits", permits identification and implementation of clock gating in IC design to reduce dynamic power consumption.

US patent 7,073,146: "Automatic assertion generation for functional validation of integrated circuits " provides a method for automatically detecting unstable clock-domain crossings in IC design and making a stability determination for a clock-domain crossing based on satisfaction of a stability function.

US patent 7,152,216: "Method, system, and computer program product for automatic insertion and correctness verification of level shifters in integrated circuits with multiple voltage domains" enables automatic insertion and verification of level shifter modules used in integrated circuits.