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Product category: Design and Development Software
News Release from: Atrenta | Subject: SpyGlass-DFT DSM
Edited by the Electronicstalk Editorial Team on 11 March 2008

Design analysis spots submicron defects

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SpyGlass-DFT DSM is designed to address the problems associated with timing closure due to at-speed DFT.

Atrenta has added the SpyGlass-DFT DSM to its SpyGlass design analysis platform The SpyGlass-DFT DSM solution accelerates design turnaround times by identifying timing closure issues caused by at-speed testing

The product offers advanced timing closure analysis and RTL testability improvement for deep submicron (DSM) defects associated with at-speed testing.

It provides accurate RTL fault coverage estimation for transition delay testing, together with diagnostics for low-fault coverage, early in the design flow, to achieve high test quality with minimum design iterations.

Kiran Vittal, Product Marketing Director for Test and Clocks products at Atrenta said "The SpyGlass-DFT DSM product is the only tool that works at RTL to identify timing closure issues caused by at-speed test logic and helps designers to minimise design iterations and meet their design schedules".

The test clocks in traditional stuck-at testing are designed to run on test equipment at frequencies lower than the system speed.

At-speed testing requires test clocks to be generated at the system speed and these clocks are often shared with functional clocks from a phase locked loop (PLL) clock source.

The additional test clocking circuitry affects functional clock skew and thus the timing closure of the design.

SpyGlass-DFT DSM is designed to address the problems associated with timing closure due to at-speed DFT.

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