Product category:
Design and Development Software
News Release from: Avant! Corporation | Subject: Star-Rail
Edited by the Electronicstalk Editorial
Team on 07 June 2001
Sign-off solution sorts submicron bugs
Avant! Corp claims that Star-Rail is the industry's first ultra deep submicron (UDSM) sign-off solution for IR drop and electromigration analysis of power distribution networks.
Avant! Corp claims that Star-Rail is the industry's first ultra deep submicron (UDSM) sign-off solution for IR drop and electromigration analysis of power distribution networks The new package has already been adopted by NEC
This article was originally published on Electronicstalk on 19 Jul 2001 at 8.00am (UK)
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Star-Rail, part of Avant!'s Milkyway-based, SinglePass-SoC flow, enables production of first-time correct chips by safeguarding against power, IR drop and electromigration problems.
"We are pleased to announce the availability of our next-generation, sign-off rail analysis solution", said Dr Paul Lo, chief operating officer (COO) of Avant! Corp.
"The key technology of Star-Rail is a high-performance engine that enables full-chip verification of a five million gate design in less than an hour - an order-of-magnitude improvement over previous generation rail analysis technologies.
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The accuracy of the analysis engine has been validated within ten percent of Star-Hspice results".
"NEC benchmarked several power network analysis tools and concluded that Star-Rail is the leading edge IR drop and electromigration analysis tool", said Yoshitada Fujinami, chief manager, System LSI Design engineering division, NEC Electron Devices.
"Star-Rail is the first EDA tool which passed NEC's performance and accuracy criteria for full-chip IR-drop analysis.
We have applied Star-Rail to several multi-million-gate real chips to prevent IR drop and EM problems.
We are delighted at how easily Star-Rail can be interfaced and integrated into our design environment and by the product's ability to handle current and next generation SoC designs".
Electromigration reduces the useful lifetime of a chip while excessive voltage drop or power dissipation causes silicon failure in shipped products.
Either problem results in the loss of millions of dollars spent designing a high-performance product and potentially larger costs due to lost market share.
Full-chip, sign-off verification with Star-Rail allows these problems to be discovered and fixed before tape-out.
Star-Rail offers hierarchical and incremental capability and can generate accurate models of hard macros for Mars-Rail and Astro-Rail for place and route.
Star-Rail has good performance in all power routing styles, including very dense mesh type and bump pad type designs, unlike other rail analysis tools in the market.
Avant!'s product supports all types of designs - memory, full-custom blocks, standard-cell-based P and R blocks, gate arrays and SoC designs.
Star-Rail supports both gate-level and transistor-level verification and offers a mixed mode for maximum flexibility.
Whether for ASIC, COT, full-custom, or SoC, Star-Rail integrates easily into a customer's design flow and handles design databases in all industry standard formats - GDSII, Milkyway or LEF/DEF.
Star-Rail is available on Sun Solaris-based workstations.
It integrates through standard interfaces, including Milkyway, GDSII, LEF/DEF, Synopsys Library, and Star-Hspice formats.
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