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Product category: Design and Development Software
News Release from: Avant! Corporation
Edited by the Electronicstalk Editorial Team on 25 January 2002

Flextronics opts for Astro

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Flextronics Semiconductor has chosen the Astro solution, Avant!'s breakthrough capability for ultra-deep-submicron (UDSM) physical design closure.

Flextronics Semiconductor has chosen the Astro solution, Avant!'s breakthrough capability for ultra-deep-submicron (UDSM) physical design closure Astro contributes advanced physical optimisation, place and route capability to Avant!'s Milkyway-based, SinglePass-SoC design closure solution

Additionally, Flextronics has increased the number of installed SinglePass seats by five fold to manage very large deep submicron SoC and leverage their tremendous design success with Avant!-based solutions.

Astro's two key advances - PhySiSys technology and the Milkyway-DUO architecture - target rapid design closure for UDSM designs.

PhySiSys technology optimises all UDSM physical effects such as optimised placement, logic resynthesis, timing, routing, clock tree synthesis, signal integrity, and power rails.

The Milkyway-DUO architecture speeds concurrent design optimisation while remaining 100% compatible with the Milkyway database and Apollo results.

Compared with Apollo-II, Astro achieves an average 10% better chip timing, a 3X faster run time advantage, and up to a 50% memory usage reduction for UDSM designs.

"For UDSM processes of 0.13um and below, physical technology effects that were 2nd or 3rd-order effects become critical to design closure.

We believe that Astro's concurrent optimisation of timing, logic, signal integrity and clocks, all based on Avant!'s silicon accurate analysis, provide the best solution to today's leading-edge design automation needs", stated Vig Sherrill, vice president and general manager of Flextronics Semiconductor.

"With our experience using Avant!'s tools and our evaluation of Astro's capabilities, we believe Astro's breakthrough technology is critical for our design process".

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