QuickLogic picks Avant! analysis tool

QuickLogic has selected Avant!'s Nova-ExploreRTL mixed-language analysis tool to automate checks of VHDL and Verilog RTL design descriptions for compliance with QuickLogic's RTL coding guidelines.

QuickLogic has selected Avant!'s Nova-ExploreRTL mixed-language analysis tool to automate checks of VHDL and Verilog RTL design descriptions for compliance with QuickLogic's RTL coding guidelines.

QuickLogic selected Nova-ExploreRTL analysis after an extensive evaluation of competitive tools.

Nova-ExploreRTL supports a comprehensive set of built-in rules, coupled with its powerful Tcl programming interface for creating custom rules, to meet the RTL coding guideline requirements of leading-edge customers like QuickLogic.

"We selected Avant!'s Nova-ExploreRTL mixed-language analysis tool to verify that our VHDL and Verilog designs meet our RTL coding guidelines", said Alan Tsun, vice-president of ESP Development Engineering at QuickLogic.

"Not only does Nova-ExploreRTL have a large set of built-in rules, but it allows us to write additional custom rules in Tcl.

Our initial set of 30 to 40 custom rules will range from simple naming convention rules to complex clock and reset rules.

We required a single, customisable analysis tool for both VHDL and Verilog RTL designs.

We found Nova-ExploreRTL to be a stable tool with a powerful, easy-to-use GUI that is productive for debugging difficult problems.

Nova-ExploreRTL will shorten our time to market and lower our development costs by speeding the synthesis, DFT, and backend integration steps with reusable code that meets our coding guidelines.

Nova-ExploreRTL will be the RTL-signoff tool between our corporate design centres".

"We are pleased that QuickLogic has chosen Nova-ExploreRTL Mixed-Language Analysis", said Dr Paul Lo, president of Avant! Corporation.

"Our Milkyway-based, SinglePass-SoC solution emphasis requires a tool that handles both Verilog and VHDL RTL blocks in support of SoC design.

The new Nova-ExploreRTL mixed-language analysis capability will further enable our customers' success in their chosen markets".

Nova-ExploreRTL mixed-language analysis has over 800 built-in Verilog and VHDL rules, divided into 13 categories including synthesis checks, simulation checks, coding style, finite-state-machine (FSM) checks, mixed clock-domain analysis, DFT conformance, and RTL design reusability.

Designs can intermix Verilog and VHDL modules at any level of hierarchy.

When used prior to logic synthesis and simulation, Nova-ExploreRTL can detect 50% or more of design errors at the RTL level.

With customised rules written in Tcl, customers can check conformance to their specific design styles and standards.

Using Nova-ExploreRTL, detection of difficult coding errors, which previously could take months, can take just minutes.

Because the quick checks are performed early in the design cycle, designers generate high-quality and reusable RTL code while reducing development time and costs.

Nova-ExploreRTL supports batch mode to automate design flows and interactive mode to quickly correct coding problems and debug difficult problems.

Nova-ExploreRTL Mixed Language Analysis 2001.4 is available on Solaris, HP U/X, and Red Hat Linux operating systems.

The US list price is $50,000.

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