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Aldec
2260 Corporate Circle
Henderson
NV 89074
USA
Latest articles from this company
News releases from this company
Design software spots problems early on
Alint gives engineers instant feedback on structural, coding and consistency problems early in the design verification cycle.
News from Electronicstalk, 1 July 2008
FPGA board prototypes space designs
Flash-based prototyping board eases application of radiation-tolerant antifuse-based RTAX-S FPGAs from Actel.
News from Electronicstalk, 15 May 2007
New interface simplifies design verification
Co-simulation support for fixed-point in Simulink simplifies verification of hardware designs in Active-HDL.
News from Electronicstalk, 12 April 2007
Third party development support for FPGAs
Active-HDL Design Flow Manager supports the Cyclone III FPGA family and provides access to Altera's Quartus II software version 7.0 and third-party synthesis tools.
News from Electronicstalk, 21 March 2007
Verification environment moves up to Stratix III
Aldec has announced System Verification Environment (SVE) support for Altera Corporation's new high-end Stratix III FPGA device family.
News from Electronicstalk, 10 November 2006
HDL simulator upgrades performance
The latest Riviera-Pro release adds high performance SLP (system level platform) technology and is an important milestone for Aldec in Verilog RTL, gate and timing simulation.
News from Electronicstalk, 17 October 2006
Expression coverage aids verification performance
Expression Coverage for Verilog is included in the latest release of Riviera.
News from Electronicstalk, 21 July 2006
SoC simulator supports IP encryption
Aldec is providing support for the Open IP Encryption Initiative design flow in the latest version of its Riviera tool.
News from Electronicstalk, 11 July 2006
Patent paves way for ASIC-to-FPGA conversion
Aldec has been awarded a new patent for automatic conversion of ASIC designs into FPGA devices.
News from Electronicstalk, 25 May 2006
Simulator works with Altera design tools
Aldec announced today that its simulator now has integrated HDL support from Altera's Quartus II version 6.0 development software environment.
News from Electronicstalk, 12 May 2006
HDL simulator supports multicore SPARC
Aldec is providing full simulation support in Riviera for the open-source UltraSPARC T1 from Sun Microsystems.
News from Electronicstalk, 5 May 2006
Manager takes charge of large-scale simulations
Software automates the setup, execution and analysis of simulation results from hundreds of computers running thousands of test cases and providing automated pass/fail results and reporting.
News from Electronicstalk, 19 April 2006
Site licence covers 10,000 HDL simulators
Aldec has signed a site licence for 10,000 Riviera HDL simulators to be installed at Renesas Design Viet Nam.
News from Electronicstalk, 17 August 2005
Simulator made for networked design verification
Riviera-SNA addresses changing customer needs as ESL and ASIC manufacturers require an increased number of high-performance simulators online.
News from Electronicstalk, 2 August 2005
New technology speeds system-level verification
The latest release of Riviera features an all new system-level simulation engine and improved SystemC debugging.
News from Electronicstalk, 19 April 2005
Coverification and debug takes on ARM hard core
Aldec has released Riviera-IPT with all-new support for the ARM926 hard-core processor including functionality for smart clocking and memory mapping.
News from Electronicstalk, 9 March 2005
Design software is made for Altera
Available now from Aldec, Active-HDL 6.3, Altera Edition features direct support and automation for Altera's Quartus II design software version 4.2, Stratix II FPGAs and HardCopy II structured ASICs.
News from Electronicstalk, 26 January 2005
Software is streamlined for SystemC
The latest release of Riviera features extended support for SystemC by allowing designers to instantiate VHDL and Verilog modules in SystemC code.
News from Electronicstalk, 29 December 2004
Software does the lot for Actel FPGAs
Aldec has released a special Actel Edition of Active-HDL 6.3, offering easy-to-use pushbutton integration with Actel's Designer series advanced place-and-route software.
News from Electronicstalk, 15 December 2004
Interface streamlines FPGA design flow
Aldec and Magma Design Automation have completed the design flow interface between Active-HDL 6.3 and Palace version 2.4.
News from Electronicstalk, 18 November 2004
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