Hardware acceleration speeds through simulation

Riviera-IPT is a unified, assertion-based hardware acceleration platform that maximises simulation performance and accelerates ASIC and FPGA design verification by 10-50x over traditional methods.

Riviera-IPT is a unified, assertion-based hardware acceleration platform that maximises simulation performance and accelerates ASIC and FPGA design verification by 10-50x over traditional methods.

Because it is based on Aldec's industry-proven VHDL and Verilog common kernel mixed-language simulator and hardware acceleration technology, Riviera-IPT is ideal for the newest devices made in 180nm technology and below and for multi-million gate system-on-chip designs.

Riviera-IPT will be demonstrated next month at the Design Automation Conference.

"Using assertions in the verification process saves customers a tremendous amount of time", said Eric Seabrook, Product Marketing Manager for Aldec.

"For larger, system-level designs, it has also become important to provide designers with a unified acceleration platform for superior efficiency.

With Riviera-IPT, our customers get VHDL, Verilog, assertion-based verification, SystemC and hardware acceleration in one seamless platform".

Riviera-IPT enhances debugging capabilities and accelerates the verification process by supporting assertions in both a software and hardware environment.

The high-level language of assertions contains powerful declarative constructs for capturing and verifying design specifications throughout the design cycle.

Additionally, using assertions in conjunction with a traditional testbench produces faster verification results and improves the overall coverage with less effort.

Assertions are portable and can be added to the design outside the unit under test (UUT) or can be embedded directly in the design during coding with Riviera-IPT.

Adding assertions to a design block will speed its verification, particularly if it contains complex algorithms and millions of gates.

In addition to handling assertions in software, Riviera-IPT has the unique ability to compile assertions into hardware, along with selected design sections.

The assertion compiler in Riviera-IPT can produce module checkers in the form of RTL code added to the synthesisable portion of the design.

Riviera-IPT can then use these assertion checks at both the behavioural (dynamic) level in the software simulator, and at the structural (static) level in the hardware accelerator.

The hardware-based assertion monitors consist of two principal parts: logical sequence of signals to be observed and the desired response when the assertion violation is detected.

Once implemented and verified, assertions can remain as part of the final design and be used as real time protocol checkers and detect violations during normal device operation.

The user can choose to compile the assertion checkers into hardware and gain extra productivity during design prototyping.

These checkers can also be used later on for monitoring the final product operation.

Riviera-IPT's common kernel architecture supports VHDL, Verilog, SystemC, assertions and acceleration.

It also handles memories and devices such as DSPs and ASICs for joint verification of legacy designs, EDIF-based IP cores, existing hardware, and HDL blocks.

By eliminating potential conflicts between verification tools, teams and design methods, Riviera-IPT is able to accelerate design verification by 10-50x.

Designers in turn save time and produce more reliable tapeouts.

Riviera-IPT enables designers to verify and optimise their designs in smaller-sized, more manageable blocks.

Each block is verified in software by Riviera-IPT's built-in, event-driven simulator to allow for total visibility and debugging of the module before it is synthesised and placed in the hardware accelerator.

After the verified module is placed in the hardware board, it remains "connected" to the remainder of the design residing in the software simulator, but eliminates the typical processing overhead.

Ultimately, the majority of the design blocks, including assertions, reside in hardware, while the behavioural testbench and SystemC components remain in software.

The interface between the components in hardware and software is managed through Riviera-IPT's Design Verification Manager (DVM), which facilitates the entire process and provides communication between the software and hardware components.

Based on Aldec's industry-proven mixed HDL verification environment, Riviera-IPT includes an IEEE VHDL, Verilog and EDIF common kernel simulator, the Design Verification Manager (DVM), a hardware accelerator board with a capacity of up to 12 million FPGA gates, and an interface to a SystemC compiler.

Optionally, Synplicity's Synplify logic synthesis may be added to complete the design flow.

The Riviera-IPT system can be configured for Unix, Linux or Windows NT/2000/XP.

Riviera-IPT will accommodate up to 12 million FPGA gates or 3 million ASIC gates.

Riviera-IPT is sold directly by Aldec in the USA and through authorised international distributors.

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