Coverification speeds soft-core FPGA designs

CoVer is a novel hardware/software coverification platform for FPGA designs using soft-core microprocessors.

Aldec has entered the embedded systems market with a hardware/software coverification platform.

The new platform, CoVer, was developed for FPGA designs using soft-core microprocessors.

By combining Aldec's proven HDL design entry and verification software, Active-HDL, with its new CoVer technology, both hardware and software teams are able to work in parallel on the same configuration of the design from day one.

Complete debugging visibility is available to both teams at all times and throughout the entire design process.

"Designers asked us for a tool that will allow concurrent hardware-software development with 10x speed improvement and visibility, and we did it", said Creighton Roethler, Product Marketing Manager for Embedded Systems.

"What's more, we did it with full synchronisation of events and cycles between hardware and software design sections".

Placing the processor and its related software into CoVer hardware, while putting all peripherals in Active-HDL, allows concurrent design verification by hardware and software teams.

During data exchange between CoVer hardware and the Active-HDL simulator, the processor executes its program at between 100 and 200kHz.

When not communicating with the peripherals in Active-HDL, the processor runs in emulation mode at 16MHz, providing complete signal visibility and ultrafast debugging at any hierarchical level of the design.

CoVer provides direct event or transaction-based communication between the hardware and software design sections allowing reliable and efficient debugging and verification.

It eliminates the need for cables, lab time, and "stub code" and does away with having to continuously make new hardware prototypes for the software team.

Working with CoVer the software team can start at the same time as the hardware team, and both teams can debug and test in parallel the same design configuration using tools that they are most comfortable with (editors, compilers, debuggers, simulators etc).

The hardware team is using a proven HDL simulator from Aldec that has a feature rich design entry and high performance simulation suite.

The inclusion of Active-HDL in the CoVer product provides the hardware team with a popular tool for design crossprobing and verification.

CoVer for the Xilinx MicroBlaze and Altera Nios processors is available now.

US pricing for Active-HDL combined with CoVer begins at $15,900 for a single licence.

Both products are available for Windows platforms.

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