Upgrade boosts verification performance

In addition to a twofold performance increase over the previous version, the latest release of Riviera includes a new advanced graphical dataflow, toggle coverage viewer and X-Trace.

In addition to a twofold performance increase over the previous version, the latest release of Riviera includes a new advanced graphical dataflow, toggle coverage viewer and X-Trace.

Riviera, a high-performance verification tool, is based on Aldec's industry-proven VHDL and Verilog mixed-language simulation technology used by ASIC and high-density FPGA designers for new generation system-on-chip designs.

Aldec has increased the behavioural, gate-level and timing simulation performance with the release of Riviera 2003.09.

Performance optimisations have yielded as much as a twofold improvement for VHDL, Verilog and mixed designs on all supported platforms.

Better memory allocation and usage in Riviera has also substantially reduced the amount required during both compilation and simulation further speeding overall run times.

The advanced graphical dataflow window allows the designer to explore the connectivity of the simulated design and analyse the dataflow among instances, concurrent statements, signals, nets and registers.

Design objects are displayed in the diagram window and can be viewed in hierarchical or flattened modes.

Toggle coverage has been improved to include a stand-alone viewer for reading the XML generated reports, previously displayed using a standard web browser.

Riviera's toggle coverage viewer offers many advantages including grouping, merge, filtering and sorting of data.

Riviera now includes the X-Trace command that creates a report with information about unknown values in the simulation model.

Each X-Trace report entry can be saved as a text or HTML file and includes simulation time, full hierarchical names of the signal that experienced an unknown value.

Riviera 2003.09 is available today based on a floating OS independent license that supports Unix, Windows and Linux.

Pricing starts at a US list price of $12,500 for a single seat/single language and is a free update for existing customers.

Riviera 2003.09 includes an industry proven mixed VHDL and Verilog simulation engine that supports IEEE VHDL 1076-87/93 and Vital 2000 in addition to Verilog 1376-95 and 2001.

Code coverage, design profiler and interfaces to other EDA tools are provided via PLI and VHPI function calls as part of Riviera's product configuration.

Riviera is sold directly by Aldec in the USA and by authorised international distributors.

A free evaluation copy of Riviera can be downloaded from the Aldec website.

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