Wizard brings Simulink and Active-HDL together

A Cosimulation Wizard for Simulink provides system designers with an advanced cosimulation solution for verification of system models developed in Simulink and digital logic developed in Active-HDL.

A new Cosimulation Wizard for Simulink provides system designers with an advanced cosimulation solution for verification of system models developed in Simulink and digital logic developed in Active-HDL.

The cosimulation enables designers to achieve more efficient and bug-free code earlier in the design cycle.

DSP functions are very efficient when implemented in FPGAs.

Many system engineers are opting to actualise their algorithms in FPGA devices instead of traditional DSPs because FPGAs are often less expensive and are also ideal for handling complex, redundant computation tasks often relegated to front-end processors.

"We are very excited about the benefits of our new Cosimulation Wizard for Simulink", commented David Rinehart, Director of Marketing for Aldec.

"Enabled by the growing densities of FPGA devices, algorithmic designs can be more effectively supported in FPGAs, making cosimulation of algorithms and HDL code increasingly valuable to support today's designs".

"We see increasing interest in the market for implementing DSP designs on FPGAs", stated Jim Tung, MathWorks Fellow at The MathWorks.

"The interface developed by Aldec extends our Simulink model-based design environment and will help designers integrate HDL components into the Simulink system models used to create those designs".

In the past, DSP designers' familiarity with software languages would often lead them to create a Matlab or Simulink model for a pre-existing HDL module to avoid the complexity associated with cosimulation.

However, the process of rewriting HDL modules as Matlab algorithms introduces additional delays in testing the overall functionality of the design.

With the availability of the Cosimulation Wizard for Simulink, system engineers can now verify all components of a design in a single environment.

Active-HDL's new Cosimulation Wizard for Simulink allows HDL components to co-exist with Simulink models, including Matlab algorithms, in a combined simulation flow.

As a result, designers can ensure that both hardware and software components are accurate and functional prior to FPGA implementation without having to rewrite HDL model or software algorithms.

Active-HDL's Cosimulation Wizard for Simulink gives DSP designers the ability to support HDL components in their design while achieving the fastest, most efficient cosimulation environment on the market.

Active-HDL's interface allows DSP designers to select HDL modules or entities that will be used as a black-box during the verification process performed within Matlab and Simulink.

The system engineer creates the system description in Simulink and uses Simulink blocks from Active-HDL's Cosimulation Wizard to represent HDL components supported as a black-box in the design.

Designers can then run cosimulations of the Simulink model, including the HDL components simulated using Active-HDL, directly within the Simulink environment.

Simulation results of the design in its entirety may then be viewed in both the Simulink and Active-HDL environments.

Active-HDL's Cosimulation Wizard for Simulink is available as part of Active-HDL 6.1.

Active-HDL customers who already own Active-HDL, and are currently under a valid maintenance contract, will receive the new Cosimulation Wizard for Simulink free of charge.

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